Noise in deep submicron digital design
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Proceedings of the 37th Annual Design Automation Conference
System power management support in the IBM POWER6 microprocessor
IBM Journal of Research and Development
Chip integration methodology for the IBM S/390 G5 and G6 custom microprocessors
IBM Journal of Research and Development
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IBM Journal of Research and Development
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IBM Journal of Research and Development
Power-constrained high-frequency circuits for the IBM POWER6 microprocessor
IBM Journal of Research and Development
Three-dimensional silicon integration
IBM Journal of Research and Development
Optimization of via distribution and stacked via in multi-layered P/G networks
Integration, the VLSI Journal
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Proceedings of the Conference on Design, Automation and Test in Europe
Design methodology for the IBM POWER7 microprocessor
IBM Journal of Research and Development
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Proceedings of the International Conference on Computer-Aided Design
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The IBM POWER6™ microprocessor is a 790 million-transistor chip that runs at a clock frequency of greater than 4 GHz. The complexity and size of the POWER6 microprocessor, together with its high operating frequency, present a number of significant challenges. This paper describes the physical design and design methodology of the POWER6 processor. Emphasis is placed on aspects of the design methodology, technology, clock distribution, integration, chip analysis, power and performance, random logic macro (RLM), and design data management processes that enabled the design to be completed and the project goals to be met.