Scheduling Processor Voltage and Frequency in Server and Cluster Systems
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 11 - Volume 12
A performance-conserving approach for reducing peak power consumption in server systems
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High-performance CMOS variability in the 65-nm regime and beyond
IBM Journal of Research and Development - Advanced silicon technology
Energyscale for IBM POWER6 microprocessor-based systems
IBM Journal of Research and Development
Power-aware dynamic placement of HPC applications
Proceedings of the 22nd annual international conference on Supercomputing
IBM POWER6 microprocessor physical design and design methodology
IBM Journal of Research and Development
Energyscale for IBM POWER6 microprocessor-based systems
IBM Journal of Research and Development
Online circuit reliability monitoring
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Optimal power allocation in server farms
Proceedings of the eleventh international joint conference on Measurement and modeling of computer systems
Temperature-constrained power control for chip multiprocessors with online model estimation
Proceedings of the 36th annual international symposium on Computer architecture
Green data centers and hot chips
Proceedings of the 46th Annual Design Automation Conference
WiDGET: Wisconsin decoupled grid execution tiles
Proceedings of the 37th annual international symposium on Computer architecture
Optimizing throughput and latency under given power budget for network packet processing
INFOCOM'10 Proceedings of the 29th conference on Information communications
NBTI-aware DVFS: a new approach to saving energy and increasing processor lifetime
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Power and thermal monitoring for the IBM system z10
IBM Journal of Research and Development
Power and thermal characterization of POWER6 system
Proceedings of the 19th international conference on Parallel architectures and compilation techniques
A monitor interconnect and support subsystem for multicore processors
Proceedings of the Conference on Design, Automation and Test in Europe
Markov Model Based Power Management in Server Clusters
GREENCOM-CPSCOM '10 Proceedings of the 2010 IEEE/ACM Int'l Conference on Green Computing and Communications & Int'l Conference on Cyber, Physical and Social Computing
Power and energy-aware processor scheduling
Proceedings of the 2nd ACM/SPEC International Conference on Performance engineering
Adaptive energy-management features of the IBM POWER 7 chip
IBM Journal of Research and Development
What computer architects need to know about memory throttling
ISCA'10 Proceedings of the 2010 international conference on Computer Architecture
Spatial and temporal thermal characterization of stacked multicore architectures
ACM Journal on Emerging Technologies in Computing Systems (JETC)
A survey of architectural techniques for DRAM power management
International Journal of High Performance Systems Architecture
A survey and taxonomy of on-chip monitoring of multicore systems-on-chip
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the Conference on Design, Automation and Test in Europe
Runtime power reduction capability of the IBM POWER7+ chip
IBM Journal of Research and Development
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The IBM POWER6™ microprocessor chip supports advanced, dynamic power management solutions for managing not, just the chip but the entire server. The design facilitates a programmable power management solution for greater flexibility and integration into system- and data-center-wide management solutions. The design of the POWER6 microprocessor provides real-time access to detailed and accurate information on power, temperature, and performance. Together, the sensing, actuation, and management support available in the POWER6 processor, known as the EnergyScale™ architecture, enables higher performance, greater energy efficiency, and new power management capabilities such as power and thermal capping and power savings with explicit performance control. This paper provides an overview of the innovative design of the POWER6 processor that enables these advanced, dynamic system power management solutions.