Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance
Proceedings of the 31st annual international symposium on Computer architecture
Aide de camp: asymmetric multi-core design for dynamic thermal management
Aide de camp: asymmetric multi-core design for dynamic thermal management
Vertigo: automatic performance-setting for Linux
OSDI '02 Proceedings of the 5th symposium on Operating systems design and implementationCopyright restrictions prevent ACM from being able to make the PDFs for this conference available for downloading
Energy conservation policies for web servers
USITS'03 Proceedings of the 4th conference on USENIX Symposium on Internet Technologies and Systems - Volume 4
A hardware architecture for dynamic performance and energy adaptation
PACS'02 Proceedings of the 2nd international conference on Power-aware computer systems
Scheduling for heterogeneous processors in server systems
Proceedings of the 2nd conference on Computing frontiers
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Analyzing the Energy-Time Trade-Off in High-Performance Computing Applications
IEEE Transactions on Parallel and Distributed Systems
VirtualPower: coordinated power management in virtualized enterprise systems
Proceedings of twenty-first ACM SIGOPS symposium on Operating systems principles
System power management support in the IBM POWER6 microprocessor
IBM Journal of Research and Development
Vpm tokens: virtual machine-aware power budgeting in datacenters
HPDC '08 Proceedings of the 17th international symposium on High performance distributed computing
VPM tokens: virtual machine-aware power budgeting in datacenters
Cluster Computing
Runtime Energy Adaptation with Low-Impact Instrumented Code in a Power-Scalable Cluster System
CCGRID '10 Proceedings of the 2010 10th IEEE/ACM International Conference on Cluster, Cloud and Grid Computing
Compiler and runtime support for predictive control of power and cooling
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Proceedings of the 2nd ACM/SPEC International Conference on Performance engineering
ReRack: power simulation for data centers with renewable energy generation
ACM SIGMETRICS Performance Evaluation Review
Adaptive energy-efficient scheduling for real-time tasks on DVS-enabled heterogeneous clusters
Journal of Parallel and Distributed Computing
Architecturally homogeneous power-performance heterogeneous multicore systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Energy saving strategies for parallel applications with point-to-point communication phases
Journal of Parallel and Distributed Computing
Dynamic Power and Thermal Management of NoC-Based Heterogeneous MPSoCs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
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Modern server farm and cluster sites consume large quantities of energy both to power and cool the machines in the site. At the same time, less power supply redundancy is offered and power companies and government officials are requesting power consumption be reduced during certain time periods. These trends lead to the requirement of responding to rapid reductions in the maximum power the site may consume. Each possible solution must respond to the new power budget before a cascading failure occurs. Available techniques include powering down some nodes or slowing all nodes in a system uniformly. This work instead examines the feasibility of slowing nodes non-uniformly in response to their performance demands. This approach provides an opportunity to reduce the performance loss caused by a reduction in the power budget. This paper uses the execution characteristics of the work currently running on each processor of the system or cluster to predict the performance of the work at the available frequency settings. The scheduling mechanism selects the lowest frequency for the processor that provides essentially all of the available performance of the work. It ensures that the frequency fits within the available global power budget and, if not, reduces it so that it does. The paper demonstrates the approach using a simple, synthetic benchmark and then validates it using additional, real-world applications.