Reducing the frequency of tag compares for low power I-cache design
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
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ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
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MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
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ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
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ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
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EDTC '97 Proceedings of the 1997 European conference on Design and Test
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VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
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ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
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Proceedings of the 36th annual international symposium on Computer architecture
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This paper proposes an architecture for low-power direct-mapped instruction caches, called "history-based tag-comparison (HBTC) cache". The HBTC cache attempts to detect and omit unnecessary tag checks at run time. Execution footprints are recorded in an extended BTB (Branch Target Buffer), and are used to know the cache residence of target instructions before starting cache access. In our simulation, it is observed that our approach can reduce the total count of tag checks by 90%, resulting in 15% of cache-energy reduction, with less than 0.5% performance degradation.