Optimizing the DRAM refresh count for merged DRAM/logic LSIs
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
ACM SIGPLAN Notices
Memory controller policies for DRAM power management
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Automatic data migration for reducing energy consumption in multi-bank memory systems
Proceedings of the 39th annual Design Automation Conference
Scheduler-based DRAM energy management
Proceedings of the 39th annual Design Automation Conference
Tuning garbage collection for reducing memory system energy in an embedded java environment
ACM Transactions on Embedded Computing Systems (TECS)
Improving memory energy using access pattern classification
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Energy savings through compression in embedded Java environments
Proceedings of the tenth international symposium on Hardware/software codesign
Compiler-Directed Array Interleaving for Reducing Energy in Multi-Bank Memories
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Online strategies for dynamic power management in systems with multiple power-saving states
ACM Transactions on Embedded Computing Systems (TECS)
DRAM Energy Management Using Sof ware and Hardware Directed Power Mode Control
HPCA '01 Proceedings of the 7th International Symposium on High-Performance Computer Architecture
Memory access scheduling and binding considering energy minimization in multi-bank memory systems
Proceedings of the 41st annual Design Automation Conference
Reducing energy consumption of queries in memory-resident database systems
Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems
Dynamic tracking of page miss ratio curve for memory management
ASPLOS XI Proceedings of the 11th international conference on Architectural support for programming languages and operating systems
Performance directed energy management for main memory and disks
ASPLOS XI Proceedings of the 11th international conference on Architectural support for programming languages and operating systems
Energy-aware variable partitioning and instruction scheduling for multibank memory architectures
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Improving energy efficiency by making DRAM less randomly accessed
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Minimizing energy consumption of banked memories using data recomputation
Proceedings of the 2006 international symposium on Low power electronics and design
Cache miss clustering for banked memory systems
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Design and implementation of power-aware virtual memory
ATEC '03 Proceedings of the annual conference on USENIX Annual Technical Conference
Limiting the power consumption of main memory
Proceedings of the 34th annual international symposium on Computer architecture
Thermal modeling and management of DRAM memory systems
Proceedings of the 34th annual international symposium on Computer architecture
Cross-component energy management: Joint adaptation of processor and memory
ACM Transactions on Architecture and Code Optimization (TACO)
Thousand core chips: a technology perspective
Proceedings of the 44th annual Design Automation Conference
Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture
Improving SDRAM access energy efficiency for low-power embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
ILP-Based energy minimization techniques for banked memories
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Software thermal management of dram memory for multicore systems
SIGMETRICS '08 Proceedings of the 2008 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
System power management support in the IBM POWER6 microprocessor
IBM Journal of Research and Development
A power and temperature aware DRAM architecture
Proceedings of the 45th annual Design Automation Conference
PowerNap: eliminating server idle power
Proceedings of the 14th international conference on Architectural support for programming languages and operating systems
Memory MISER: Improving Main Memory Energy Efficiency in Servers
IEEE Transactions on Computers
Mini-rank: Adaptive DRAM architecture for improving memory power efficiency
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Memory Systems: Cache, DRAM, Disk
Memory Systems: Cache, DRAM, Disk
Decoupled DIMM: building high-bandwidth memory system using low-speed DRAM devices
Proceedings of the 36th annual international symposium on Computer architecture
PPT: joint performance/power/thermal management of DRAM memory for multi-core systems
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Future scaling of processor-memory interfaces
Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis
IBM memory expansion technology (MXT)
IBM Journal of Research and Development
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Online memory compression for embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
Micro-pages: increasing DRAM efficiency with locality-aware data placement
Proceedings of the fifteenth edition of ASPLOS on Architectural support for programming languages and operating systems
Self-optimization of performance-per-watt for interleaved memory systems
HiPC'07 Proceedings of the 14th international conference on High performance computing
Rethinking DRAM design and organization for energy-constrained multi-cores
Proceedings of the 37th annual international symposium on Computer architecture
RAPL: memory power estimation and capping
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Energy efficient proactive thermal management in memory subsystem
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Rank-aware cache replacement and write buffering to improve DRAM energy efficiency
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Power and Performance Trade-Offs in Contemporary DRAM System Designs for Multicore Processors
IEEE Transactions on Computers
Heterogeneous Mini-rank: Adaptive, Power-Efficient Memory Architecture
ICPP '10 Proceedings of the 2010 39th International Conference on Parallel Processing
Understanding the Energy Consumption of Dynamic Random Access Memories
MICRO '43 Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
Elastic Refresh: Techniques to Mitigate Refresh Penalties in High Density Memory
MICRO '43 Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
Flikker: saving DRAM refresh-power through critical data partitioning
Proceedings of the sixteenth international conference on Architectural support for programming languages and operating systems
MemScale: active low-power modes for main memory
Proceedings of the sixteenth international conference on Architectural support for programming languages and operating systems
Coordinating processor and main memory for efficientserver power control
Proceedings of the international conference on Supercomputing
Memory power management via dynamic voltage/frequency scaling
Proceedings of the 8th ACM international conference on Autonomic computing
Adaptive granularity memory systems: a tradeoff between storage efficiency and throughput
Proceedings of the 38th annual international symposium on Computer architecture
Hardware/software techniques for DRAM thermal management
HPCA '11 Proceedings of the 2011 IEEE 17th International Symposium on High Performance Computer Architecture
Energy-Efficient value-based selective refresh for embedded DRAMs
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Minimalist open-page: a DRAM page-mode scheduling policy for the many-core era
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
System level multi-bank main memory configuration for energy reduction
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
What computer architects need to know about memory throttling
ISCA'10 Proceedings of the 2010 international conference on Computer Architecture
MORSE: Multi-objective reconfigurable self-optimizing memory scheduler
HPCA '12 Proceedings of the 2012 IEEE 18th International Symposium on High-Performance Computer Architecture
Proceedings of the 49th Annual Design Automation Conference
Run-time power-down strategies for real-time SDRAM memory controllers
Proceedings of the 49th Annual Design Automation Conference
High-performance and low-power memory-interface architecture for video processing applications
IEEE Transactions on Circuits and Systems for Video Technology
MultiScale: memory system DVFS with multiple memory controllers
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
RAIDR: Retention-Aware Intelligent DRAM Refresh
Proceedings of the 39th Annual International Symposium on Computer Architecture
BOOM: enabling mobile memory based low-power server DIMMs
Proceedings of the 39th Annual International Symposium on Computer Architecture
Towards energy-proportional datacenter memory with mobile DRAM
Proceedings of the 39th Annual International Symposium on Computer Architecture
LOT-ECC: localized and tiered reliability mechanisms for commodity memory systems
Proceedings of the 39th Annual International Symposium on Computer Architecture
Barely alive memory servers: Keeping data active in a low-power state
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Tiered Memory: An Iso-Power Memory Architecture to Address the Memory Power Wall
IEEE Transactions on Computers
| Hi-index | 0.00 |
Recent trends of CMOS technology scaling and wide-spread use of multicore processors have dramatically increased the power consumption of main memory. It has been estimated that modern data-centres spend more than 30% of their total power consumption in main memory alone. This excessive power dissipation has created the problem of 'memory power wall' which has emerged as a major design constraint inhibiting further performance scaling. Recently, several techniques have been proposed to address this issue. The focus of this paper is to survey several architectural techniques designed for improving power efficiency of main memory systems, specifically DRAM systems. To help the reader in gaining insights into the similarities and differences between the techniques, this paper also presents a classification of the techniques on the basis of their characteristics. The aim of this paper is to equip the engineers and architects with knowledge of the state of the art DRAM power saving techniques and motivate them to design novel solutions for addressing the challenges presented by the memory power wall problem.