Operating-system directed power reduction
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Energy-oriented compiler optimizations for partitioned memory architectures
CASES '00 Proceedings of the 2000 international conference on Compilers, architecture, and synthesis for embedded systems
ASPLOS IX Proceedings of the ninth international conference on Architectural support for programming languages and operating systems
Memory controller policies for DRAM power management
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Online strategies for dynamic power management in systems with multiple power-saving states
ACM Transactions on Embedded Computing Systems (TECS)
DRAM Energy Management Using Sof ware and Hardware Directed Power Mode Control
HPCA '01 Proceedings of the 7th International Symposium on High-Performance Computer Architecture
Power Aware Variable Partitioning and Instruction Scheduling for Multiple Memory Banks
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Dynamic tracking of page miss ratio curve for memory management
ASPLOS XI Proceedings of the 11th international conference on Architectural support for programming languages and operating systems
Improving energy efficiency by making DRAM less randomly accessed
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
DRAMsim: a memory system simulator
ACM SIGARCH Computer Architecture News - Special issue: dasCMP'05
Limiting the power consumption of main memory
Proceedings of the 34th annual international symposium on Computer architecture
Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture
An approach for adaptive DRAM temperature and power management
Proceedings of the 22nd annual international conference on Supercomputing
Mini-rank: Adaptive DRAM architecture for improving memory power efficiency
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
DRAM power-aware rank scheduling
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
RAMZzz: rank-aware dram power management with dynamic migrations and demotions
SC '12 Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis
A survey of architectural techniques for DRAM power management
International Journal of High Performance Systems Architecture
XDRA: exploration and optimization of last-level cache for energy reduction in DDR DRAMs
Proceedings of the 50th Annual Design Automation Conference
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DRAM power and energy efficiency considerations are becoming increasingly important for low-power and mobile systems. Using lower power modes provided by commodity DRAM chips reduces power consumption but comes at a performance penalty to return to full power for servicing requests. We propose a novel cache replacement policy and write buffer that prevents cache blocks going to certain DRAM chips from being replaced, resulting in less requests going to these chips, and allowing them to remain idle for longer periods of time. Our proposed modifications improve DRAM energy efficiency by 10% on average (up to 30%) compared to a base case that utilizes low power modes, and by 76% compared to a base case that does not utilize power saving modes.