Memory controller policies for DRAM power management
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Custom Memory Management Methodology: Exploration of Memory Organisation for Embedded Multimedia System Design
Efficient Global Optimization of Expensive Black-Box Functions
Journal of Global Optimization
ACM Transactions on Embedded Computing Systems (TECS)
DRAM Energy Management Using Sof ware and Hardware Directed Power Mode Control
HPCA '01 Proceedings of the 7th International Symposium on High-Performance Computer Architecture
Memory access scheduling and binding considering energy minimization in multi-bank memory systems
Proceedings of the 41st annual Design Automation Conference
Design space exploration of caches using compressed traces
Proceedings of the 18th annual international conference on Supercomputing
Improving energy efficiency by making DRAM less randomly accessed
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
DRAMsim: a memory system simulator
ACM SIGARCH Computer Architecture News - Special issue: dasCMP'05
Compiler-directed channel allocation for saving power in on-chip networks
Conference record of the 33rd ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Computer Architecture, Fourth Edition: A Quantitative Approach
Computer Architecture, Fourth Edition: A Quantitative Approach
PABC: Power-Aware Buffer Cache Management for Low Power Consumption
IEEE Transactions on Computers
Improving SDRAM access energy efficiency for low-power embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
An approach for adaptive DRAM temperature and power management
Proceedings of the 22nd annual international conference on Supercomputing
Response surface methodology for simulating hedging and trading strategies
Proceedings of the 40th Conference on Winter Simulation
Mini-rank: Adaptive DRAM architecture for improving memory power efficiency
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
A correlation-based design space exploration methodology for multi-processor systems-on-chip
Proceedings of the 47th Design Automation Conference
Rank-aware cache replacement and write buffering to improve DRAM energy efficiency
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
DEW: a fast level 1 cache simulation approach for embedded processors with FIFO replacement policy
Proceedings of the Conference on Design, Automation and Test in Europe
Realizing Cycle Accurate Processor Memory Simulation via Interface Abstraction
VLSID '11 Proceedings of the 2011 24th International Conference on VLSI Design
Fast configurable-cache tuning with a unified second-level cache
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Improved Power Modeling of DDR SDRAMs
DSD '11 Proceedings of the 2011 14th Euromicro Conference on Digital System Design
Design space exploration of workload-specific last-level caches
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
A Predictor-Based Power-Saving Policy for DRAM Memories
DSD '12 Proceedings of the 2012 15th Euromicro Conference on Digital System Design
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Embedded systems with high energy consumption often exploit the idleness of DDR-DRAM to reduce their energy consumption by putting the DRAM into deepest low-power mode (self-refresh power down mode) during idle periods. DDR-DRAM idle periods heavily depend on the last-level cache. Exhaustive search using processor-memory simulators can take several months. This paper for first time proposes a fast framework called XDRA, which allows the exploration of last-level cache configurations to improve DDR-DRAM energy efficiency. XDRA combines a processor-memory simulator, a cache simulator and novel analysis techniques to produce a Kriging based estimator which predicts the energy savings for differing cache configurations for a given main memory size and application. Errors for the estimator were less than 4.4% on average for 11 applications from mediabench and SPEC2000 suite and two DRAM sizes (Micron DDR3-DRAM 256MB and 4GB). Cache configurations selected by XDRA were on average 3.6x and 4x more energy efficient (cache and DRAM energy) than a common cache configuration. Optimal cache configurations were selected by XDRA 20 times out of 22. The two suboptimal configurations were at most 3.9% from their optimal counterparts. XDRA took a few days for the exploration of 330 cache configurations compared to several hundred days of cycle-accurate simulations, saving at least 85% of exploration time.