ASPLOS IX Proceedings of the ninth international conference on Architectural support for programming languages and operating systems
Memory controller policies for DRAM power management
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Hardware and Software Techniques for Controlling DRAM Power Modes
IEEE Transactions on Computers
Scheduler-based DRAM energy management
Proceedings of the 39th annual Design Automation Conference
Power-Aware Storage Cache Management
IEEE Transactions on Computers
Improving energy efficiency by making DRAM less randomly accessed
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Design and implementation of power-aware virtual memory
ATEC '03 Proceedings of the annual conference on USENIX Annual Technical Conference
DULO: an effective buffer cache management scheme to exploit both temporal and spatial locality
FAST'05 Proceedings of the 4th conference on USENIX Conference on File and Storage Technologies - Volume 4
OSDI'00 Proceedings of the 4th conference on Symposium on Operating System Design & Implementation - Volume 4
Software–hardware cooperative power management for main memory
PACS'04 Proceedings of the 4th international conference on Power-Aware Computer Systems
Analysis of power-aware buffering schemes in wireless sensor networks
ACM Transactions on Sensor Networks (TOSN)
Proceedings of the sixth conference on Computer systems
An adaptive energy-conserving strategy for parallel disk systems
Future Generation Computer Systems
Rigorous rental memory management for embedded systems
ACM Transactions on Embedded Computing Systems (TECS) - Special section on ESTIMedia'12, LCTES'11, rigorous embedded systems design, and multiprocessor system-on-chip for cyber-physical systems
XDRA: exploration and optimization of last-level cache for energy reduction in DDR DRAMs
Proceedings of the 50th Annual Design Automation Conference
IAMEM: interaction-aware memory energy management
USENIX ATC'13 Proceedings of the 2013 USENIX conference on Annual Technical Conference
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Power consumed by memory systems becomes a serious issue as the size of the memory installed increases. With various low power modes that can be applied to each memory unit, the operating system can reduce the number of active memory units by collocating active pages onto a few memory units. This paper presents a memory management scheme based on this observation, which differs from other approaches in that all of the memory space is considered, while previous methods deal only with pages mapped to user address spaces. The buffer cache usually takes more than half of the total memory and the pages access patterns are different from those in user address spaces. Based on an analysis of buffer cache behavior and its interaction with the user space, our scheme achieves up to 63 percent more power reduction. Migrating a page to a different memory unit increases memory latencies, but it is shown to reduce the power consumed by an additional 4.4 percent.