Comparing algorithm for dynamic speed-setting of a low-power CPU
MobiCom '95 Proceedings of the 1st annual international conference on Mobile computing and networking
MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Scheduling techniques for reducing processor energy use in MacOS
Wireless Networks - Special issue: mobile computing and networking: selected papers from MobiCom '96
Power optimization of variable voltage core-based systems
DAC '98 Proceedings of the 35th annual Design Automation Conference
Power conscious fixed priority scheduling for hard real-time systems
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Influence of compiler optimizations on system power
Proceedings of the 37th Annual Design Automation Conference
The design and use of simplepower: a cycle-accurate energy estimation tool
Proceedings of the 37th Annual Design Automation Conference
Energy-driven integrated hardware-software optimizations using SimplePower
Proceedings of the 27th annual international symposium on Computer architecture
A survey of design techniques for system-level dynamic power management
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low-power electronics and design
Operating-system directed power reduction
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
ASPLOS IX Proceedings of the ninth international conference on Architectural support for programming languages and operating systems
Hardware and Software Techniques for Controlling DRAM Power Modes
IEEE Transactions on Computers
Linux Kernel Internals
Custom Memory Management Methodology: Exploration of Memory Organisation for Embedded Multimedia System Design
Xtream-Fit: an energy-delay efficient data memory subsystem for embedded media processing
Proceedings of the 40th annual Design Automation Conference
Power Aware Variable Partitioning and Instruction Scheduling for Multiple Memory Banks
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Time-Energy Design Space Exploration for Multi-Layer Memory Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Access Pattern Restructuring for Memory Energy
IEEE Transactions on Parallel and Distributed Systems
Energy-aware demand paging on NAND flash-based embedded storages
Proceedings of the 2004 international symposium on Low power electronics and design
Dynamic tracking of page miss ratio curve for memory management
ASPLOS XI Proceedings of the 11th international conference on Architectural support for programming languages and operating systems
Exploring the Energy-Time Tradeoff in High-Performance Computing
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 11 - Volume 12
Energy-aware variable partitioning and instruction scheduling for multibank memory architectures
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Using multiple energy gears in MPI programs on a power-scalable cluster
Proceedings of the tenth ACM SIGPLAN symposium on Principles and practice of parallel programming
Hierarchical power management with application to scheduling
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Improving energy efficiency by making DRAM less randomly accessed
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
A page fault equation for modeling the effect of memory size
Performance Evaluation
ZettaRAM: A Power-Scalable DRAM Alternative through Charge-Voltage Decoupling
IEEE Transactions on Computers
Dynamic power management of DRAM using accessed physical addresses
Microprocessors & Microsystems
Performance-directed energy management using BOS
ACM SIGOPS Operating Systems Review
Design and implementation of power-aware virtual memory
ATEC '03 Proceedings of the annual conference on USENIX Annual Technical Conference
PABC: Power-Aware Buffer Cache Management for Low Power Consumption
IEEE Transactions on Computers
Analyzing the Energy-Time Trade-Off in High-Performance Computing Applications
IEEE Transactions on Parallel and Distributed Systems
Cross-component energy management: Joint adaptation of processor and memory
ACM Transactions on Architecture and Code Optimization (TACO)
Reducing display power in DVS-enabled handheld systems
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
A power and temperature aware DRAM architecture
Proceedings of the 45th annual Design Automation Conference
Entry control in network-on-chip for memory power reduction
Proceedings of the 13th international symposium on Low power electronics and design
Mini-rank: Adaptive DRAM architecture for improving memory power efficiency
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
System-level integrated power management for handheld systems
Microprocessors & Microsystems
PDRAM: a hybrid PRAM and DRAM main memory system
Proceedings of the 46th Annual Design Automation Conference
Energy aware scheduling on desktop grid environment with static performance prediction
SpringSim '09 Proceedings of the 2009 Spring Simulation Multiconference
Self-optimization of performance-per-watt for interleaved memory systems
HiPC'07 Proceedings of the 14th international conference on High performance computing
Rethinking DRAM design and organization for energy-constrained multi-cores
Proceedings of the 37th annual international symposium on Computer architecture
DRAM energy reduction by prefetching-based memory traffic clustering
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Memory power management via dynamic voltage/frequency scaling
Proceedings of the 8th ACM international conference on Autonomic computing
Software–hardware cooperative power management for main memory
PACS'04 Proceedings of the 4th international conference on Power-Aware Computer Systems
Handheld system energy reduction by OS-driven refresh
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Survey of scheduling techniques for addressing shared resources in multicore processors
ACM Computing Surveys (CSUR)
ViPZonE: OS-level memory variability-driven physical address zoning for energy savings
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
RAMZzz: rank-aware dram power management with dynamic migrations and demotions
SC '12 Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis
A survey of architectural techniques for DRAM power management
International Journal of High Performance Systems Architecture
A framework for application guidance in virtual memory systems
Proceedings of the 9th ACM SIGPLAN/SIGOPS international conference on Virtual execution environments
IAMEM: interaction-aware memory energy management
USENIX ATC'13 Proceedings of the 2013 USENIX conference on Annual Technical Conference
Adaptive wear-leveling algorithm for PRAM main memory with a DRAM buffer
ACM Transactions on Embedded Computing Systems (TECS)
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Previous work on DRAM power-mode management focused on hardware-based techniques and compiler-directed schemes to explicitly transition unused memory modules to low-power operating modes. While hardware-based techniques require extra logic to keep track of memory references and make decisions about future mode transitions, compiler-directed schemes can only work on a single application at a time and demand sophisticated program analysis support. In this work, we present an operating system (OS) based solution where the OS scheduler directs the power mode transitions by keeping track of module accesses for each process in the system. This global view combined with the flexibility of a software approach brings large energy savings at no extra hardware cost. Our implementation using a full-fledged OS shows that the proposed technique is also very robust when different system and workload parameters are modified, and provides the first set of experimental results for memory energy optimization with a multiprogrammed workload on a real platform. The proposed technique is applicable to both embedded systems and high-end computing platforms.