Exploiting dual data-memory banks in digital signal processors
Proceedings of the seventh international conference on Architectural support for programming languages and operating systems
Low-power task scheduling for multiple devices
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
Simultaneous reference allocation in code generation for dual data memory bank ASIPs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Minimizing the required memory bandwidth in VLSI system realizations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A recursive algorithm for low-power memory partitioning
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Optimized address assignment for DSPs with SIMD memory accesses
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Hardware and Software Techniques for Controlling DRAM Power Modes
IEEE Transactions on Computers
Proceedings of the joint conference on Languages, compilers and tools for embedded systems: software and compilers for embedded systems
Automatic data migration for reducing energy consumption in multi-bank memory systems
Proceedings of the 39th annual Design Automation Conference
Scheduler-based DRAM energy management
Proceedings of the 39th annual Design Automation Conference
Custom Memory Management Methodology: Exploration of Memory Organisation for Embedded Multimedia System Design
Variable partitioning for dual memory bank DSPs
ICASSP '01 Proceedings of the Acoustics, Speech, and Signal Processing, 200. on IEEE International Conference - Volume 02
Journal of Systems and Software
An Efficient Code Generation Algorithm for Non-orthogonal DSP Architecture
Journal of VLSI Signal Processing Systems
Automatic memory partitioning and scheduling for throughput and power optimization
Proceedings of the 2009 International Conference on Computer-Aided Design
Rank-aware cache replacement and write buffering to improve DRAM energy efficiency
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Automatic memory partitioning and scheduling for throughput and power optimization
ACM Transactions on Design Automation of Electronic Systems (TODAES)
ViPZonE: OS-level memory variability-driven physical address zoning for energy savings
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
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Many high-end DSP processors employ both multiple memory banks and heterogeneous register files to improve performance and power consumption. The complexity of such architectures presents a great challenge to compiler design. In this paper, we present an approach for variable partitioning and instruction scheduling to maximally exploit the benefits provided by such architectures. Our approach is built on a novel graph model which strives to capture both performance and power demands. We propose an algorithm to iteratively find the variable partition such that the maximum energy saving is achieved while satisfying the given performance constraint. Experimental results demonstrate the effectiveness of our approach.