DAC '98 Proceedings of the 35th annual Design Automation Conference
Global multimedia system design exploration using accurate memory organization feedback
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Interactive co-design of high throughput embedded multimedia
Proceedings of the 37th Annual Design Automation Conference
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
A decade of reconfigurable computing: a visionary retrospective
Proceedings of the conference on Design, automation and test in Europe
Data and memory optimization techniques for embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
System-level interconnect architecture exploration for custom memory organizations
Proceedings of the 14th international symposium on Systems synthesis
Proceedings of the 14th international symposium on Systems synthesis
Low power storage cycle budget distribution tool support for hierarchical graphs
ISSS '00 Proceedings of the 13th international symposium on System synthesis
Design of a high-throughput low-power IS95 Viterbi decoder
Proceedings of the 39th annual Design Automation Conference
An integrated algorithm for memory allocation and assignment in high-level synthesis
Proceedings of the 39th annual Design Automation Conference
Data Memory Organization and Optimizations in Application-Specific Systems
IEEE Design & Test
Memory Architectures for Embedded Systems-On-Chip
HiPC '02 Proceedings of the 9th International Conference on High Performance Computing
A network flow approach to memory bandwidth utilization in embedded DSP core processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Memory allocation and mapping in high-level synthesis: an integrated approach
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
Power Aware Variable Partitioning and Instruction Scheduling for Multiple Memory Banks
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Optimizing the memory bandwidth with loop fusion
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Energy-aware variable partitioning and instruction scheduling for multibank memory architectures
ACM Transactions on Design Automation of Electronic Systems (TODAES)
COSMECA: application specific co-synthesis of memory and communication architectures for MPSoC
Proceedings of the conference on Design, automation and test in Europe: Proceedings
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
A compiler approach to managing storage and memory bandwidth in configurable architectures
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Slack allocation based co-synthesis and optimization of bus and memory architectures for MPSoCs
Proceedings of the conference on Design, automation and test in Europe
Loop scheduling and bank type assignment for heterogeneous multi-bank memory
Journal of Parallel and Distributed Computing
Optimal periodic memory allocation for image processing with multiple windows
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Variable assignment and instruction scheduling for processor with multi-module memory
Microprocessors & Microsystems
Design of a 20-Mb/s 256-state viterbi decoder
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Embedded Systems Design
Improving the memory bandwidth utilization using loop transformations
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
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In this paper, we present the problem of storage bandwidth optimization (SBO) in VLSI system realizations. Our goal is to minimize the required memory bandwidth within the given cycle budget by adding ordering constraints to the flow graph. This allows the subsequent memory allocation and assignment tasks to come up with a cheaper memory architecture with less memories and memory ports. The importance and the effect of SBO is shown on realistic examples both in the video and asynchronous transfer-mode (ATM) domains. We show that it is important to take into account which data is being accessed in parallel, instead of only considering the number of simultaneous memory accesses. Our problem formulation leads to the optimization of a conflict (hyper) graph. For the target domain of ATM, only flat graphs without loops have to be treated. For this subproblem, a prototype tool has been implemented to demonstrate the feasibility of automating this important system design step.