Image Analysis Using Mathematical Morphology
IEEE Transactions on Pattern Analysis and Machine Intelligence
Theoretical Aspects of Gray-Level Morphology
IEEE Transactions on Pattern Analysis and Machine Intelligence
Morphologically Constrained GRFs: Applications to Texture Synthesis and Analysis
IEEE Transactions on Pattern Analysis and Machine Intelligence
Low-power memory mapping through reducing address bus activity
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Memory bank customization and assignment in behavioral synthesis
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Minimizing the required memory bandwidth in VLSI system realizations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Architectural exploration for datapaths with memory hierarchy
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Memory allocation and mapping in high-level synthesis: an integrated approach
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
Real-Time Connectivity Constrained Depth Map Computation Using Programmable Graphics Hardware
CVPR '05 Proceedings of the 2005 IEEE Computer Society Conference on Computer Vision and Pattern Recognition (CVPR'05) - Volume 1 - Volume 01
IEEE Micro
Architecture of a Stereo Matching VLSI Processor Based on Hierarchically Parallel Memory Access
IEICE - Transactions on Information and Systems
| Hi-index | 0.01 |
One major issue in designing image processors is to design a memory system that supports parallel access with a simple interconnection network. This paper presents an efficient memory allocation to minimize the number of memory modules and processing elements with a parallel access capability when multiple windows with arbitrary shapes are specified. This paper also presents an efficient search method based on regularity of window-type image processing. We give some practical examples including a stereo-matching processor for acquiring 3-D information, and an optical-flow processor for motion estimation. These examples show that the numbers of memory modules are reduced to 2.7% and 10%, respectively, in comparison with a basic approach. It is also shown that the search time is less than 1 ms for practical image sizes and window sizes.