Architecture of a Stereo Matching VLSI Processor Based on Hierarchically Parallel Memory Access

Authors:
Masanori Hariyama;Haruka Sasaki;Michitaka Kameyama
Affiliations:
The authors are with the Graduate School of Information Sciences, Tohoku University, Sendai-shi, 980--8579 Japan. E-mail: hariyama@ecei.tohoku.ac.jp;The authors are with the Graduate School of Information Sciences, Tohoku University, Sendai-shi, 980--8579 Japan. E-mail: hariyama@ecei.tohoku.ac.jp;The authors are with the Graduate School of Information Sciences, Tohoku University, Sendai-shi, 980--8579 Japan. E-mail: hariyama@ecei.tohoku.ac.jp
Venue:
IEICE - Transactions on Information and Systems
Year:
2005

Citing 0
Cited 2

Memory Allocation for Multi-Resolution Image Processing

IEICE - Transactions on Information and Systems
Optimal periodic memory allocation for image processing with multiple windows

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

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Abstract

This paper presents a VLSI processor for high-speed and reliable stereo matching based on adaptive window-size control of SAD(Sum of Absolute Differences) computation. To reduce its computational complexity, SADs are computed using multi-resolution images. Parallel memory access is essential for highly parallel image processing. For parallel memory access, this paper also presents an optimal memory allocation that minimizes the hardware amount under the condition of parallel memory access at specified resolutions.