Specification and design of embedded systems
Specification and design of embedded systems
Storage assignment to decrease code size
PLDI '95 Proceedings of the ACM SIGPLAN 1995 conference on Programming language design and implementation
Register allocation and binding for low power
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Address calculation for retargetable compilation and exploration of instruction-set architectures
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Time-constrained code compaction for DSP's
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 27th annual international symposium on Computer architecture
Minimizing the required memory bandwidth in VLSI system realizations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Data and memory optimization techniques for embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Current consumption dynamics at instruction and program level for a VLIW DSP processor
Proceedings of the 14th international symposium on Systems synthesis
Code Generation for Embedded Processors
Code Generation for Embedded Processors
Constraint analysis for DSP code generation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A minimum-cost circulation approach to DSP address-code generation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design of secure cryptography against the threat of power-attacks in DSP-embedded processors
ACM Transactions on Embedded Computing Systems (TECS)
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This paper presents a network flow approach to solving the register binding and allocation problem for multiword memory access DSP processors. In recently announced DSP processors, 16-bit instructions which simultaneously access four words from memory are supported. A polynomial-time network flow methodology is used to allocate multiword accesses, including constant data-memory layout, while minimizing code size. Results show that improvements of up to 87% in terms of memory bandwidth are obtained compared to compiler-generated DSP code. This research is important for industry since this value-added technique can improve code size and utilize higher-memory bandwidths without increasing cost.