Register allocation and binding for low power

Power minimization in IC design: principles and applications

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Module assignment for low power

EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation

Scheduling techniques for variable voltage low power designs

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Low energy memory and register allocation using network flow

DAC '97 Proceedings of the 34th annual Design Automation Conference

High-level power modeling, estimation, and optimization

DAC '97 Proceedings of the 34th annual Design Automation Conference

Architectural and compiler support for energy reduction in the memory hierarchy of high performance microprocessors

ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design

A new parameterizable power macro-model for datapath components

DATE '99 Proceedings of the conference on Design, automation and test in Europe

Global register allocation for minimizing energy consumption

ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design

Lower and upper bounds on the switching activity in scheduled data flow graphs

ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design

Behavioral-level partitioning for low power design in control-dominated application

GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI

A predictive system shutdown method for energy saving of event-driven computation

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Synthesis-for-testability of controller-datapath pairs that use gated clocks

Proceedings of the 37th Annual Design Automation Conference

Hybrid global/local search strategies for dynamic voltage scaling in embedded multiprocessors

Proceedings of the ninth international symposium on Hardware/software codesign

Retargetable compilation for low power

Proceedings of the ninth international symposium on Hardware/software codesign

An Accurate Instruction-Level Energy Consumption Model for Embedded RISC Processors

OM '01 Proceedings of the 2001 ACM SIGPLAN workshop on Optimization of middleware and distributed systems

Conditional speculation and its effects on performance and area for high-level snthesis

Proceedings of the 14th international symposium on Systems synthesis

Compiler optimization on instruction scheduling for low power

ISSS '00 Proceedings of the 13th international symposium on System synthesis

A joint power/performance optimization algorithm for multiprocessor systems using a period graph construct

ISSS '00 Proceedings of the 13th international symposium on System synthesis

Lower bound estimation for low power high-level synthesis

ISSS '00 Proceedings of the 13th international symposium on System synthesis

Efficient global register allocation for minimizing energy consumption

ACM SIGPLAN Notices

Early evaluation techniques for low power binding

Proceedings of the 2002 international symposium on Low power electronics and design

Bus optimization for low-power data path synthesis based on network flow method

Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design

An integrated data path optimization for low power based on network flow method

Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design

Reordering Memory Bus Transactions for Reduced Power Consumption

LCTES '00 Proceedings of the ACM SIGPLAN Workshop on Languages, Compilers, and Tools for Embedded Systems

Compiler optimization on VLIW instruction scheduling for low power

ACM Transactions on Design Automation of Electronic Systems (TODAES)

A comprehensive high-level synthesis system for control-flow intensive behaviors

Proceedings of the 13th ACM Great Lakes symposium on VLSI

A network flow approach to memory bandwidth utilization in embedded DSP core processors

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Interconnect-aware high-level synthesis for low power

Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design

Predictability: definition, ananlysis and optimization

Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design

Coupling-aware high-level interconnect synthesis for low power

Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design

Accurate high level datapath power estimation

EDTC '97 Proceedings of the 1997 European conference on Design and Test

A Game-Theoretic Approach for Binding in Behavioral Synthesis

VLSID '03 Proceedings of the 16th International Conference on VLSI Design

Quality of EDA CAD Tools: Definitions, Metrics and Directions

ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design

Synthesis of low-power selectively-clocked systems from high-level specification

ISSS '96 Proceedings of the 9th international symposium on System synthesis

Effective graph theoretic techniques for the generalized low power binding problem

Proceedings of the 2003 international symposium on Low power electronics and design

High-level synthesis for low power based on network flow method

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)

High-level macro-modeling and estimation techniques for switching activity and power consumption

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

High level techniques for power-grid noise immunity

Proceedings of the 14th ACM Great Lakes symposium on VLSI

Achieving Design Closure Through Delay Relaxation Parameter

Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design

Binding, Allocation and Floorplanning in Low Power High-Level Synthesis

Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design

A thread partitioning algorithm in low power high-level synthesis

Proceedings of the 2004 Asia and South Pacific Design Automation Conference

Voltage scheduling under unpredictabilities: a risk management paradigm

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Temperature-aware resource allocation and binding in high-level synthesis

Proceedings of the 42nd annual Design Automation Conference

Peak temperature control and leakage reduction during binding in high level synthesis

ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design

A sink-n-hoist framework for leakage power reduction

Proceedings of the 5th ACM international conference on Embedded software

Simultaneous floorplanning and resource binding: a probabilistic approach

Proceedings of the 2005 Asia and South Pacific Design Automation Conference

Optimal module and voltage assignment for low-power

Proceedings of the 2005 Asia and South Pacific Design Automation Conference

Effective techniques for the generalized low-power binding problem

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Compilers for leakage power reduction

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Loop scheduling with timing and switching-activity minimization for VLIW DSP

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Optimal simultaneous module and multivoltage assignment for low power

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Optimality study of resource binding with multi-Vdds

Proceedings of the 43rd annual Design Automation Conference

Thermal-aware high-level synthesis based on network flow method

CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis

Thermal-induced leakage power optimization by redundant resource allocation

Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design

Platform-based resource binding using a distributed register-file microarchitecture

Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design

Low Power VLSI Design Techniques - The Current State

Integrated Computer-Aided Engineering

Compilation for compact power-gating controls

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Early planning for clock skew scheduling during register binding

Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design

Behavioral synthesis with activating unused flip-flops for reducing glitch power in FPGA

Proceedings of the 2008 Asia and South Pacific Design Automation Conference

REWIRED: REgister Write Inhibition by REsource Dedication

Proceedings of the 2008 Asia and South Pacific Design Automation Conference

Algorithms and analysis of scheduling for loops with minimum switching

International Journal of Computational Science and Engineering

Algorithms and analysis of scheduling for low-power high-performance DSP on VLIW processors

International Journal of High Performance Computing and Networking

Simultaneous FU and register binding based on network flow method

Proceedings of the conference on Design, automation and test in Europe

Peak temperature control in thermal-aware behavioral synthesis through allocating the number of resources

Proceedings of the 2009 Asia and South Pacific Design Automation Conference

Simultaneous resource binding and interconnection optimization based on a distributed register-file microarchitecture

ACM Transactions on Design Automation of Electronic Systems (TODAES)

An integrated approach to thermal management in high-level synthesis

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Energy-Aware Loop Scheduling and Assignment for Multi-Core, Multi-Functional-Unit Architecture

Journal of Signal Processing Systems

FPGA-targeted high-level binding algorithm for power and area reduction with glitch-estimation

Proceedings of the 46th Annual Design Automation Conference

Scheduling with multiple voltages

Integration, the VLSI Journal

Behavioral level dual-Vth design for reduced leakage power with thermal awareness

Proceedings of the Conference on Design, Automation and Test in Europe

Power aware SID-based simulator for embedded multicore DSP subsystems

CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis

Power-driven simultaneous resource binding and floorplanning: a probabilistic approach

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Software-level instruction-cache leakage reduction using value-dependence of SRAM leakage in nanometer technologies

Transactions on high-performance embedded architectures and compilers III

A game theoretic approach for power optimization during behavioral synthesis

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Compiler analysis and supports for leakage power reduction on microprocessors

LCPC'02 Proceedings of the 15th international conference on Languages and Compilers for Parallel Computing

Power devil: tool for power gating strategy selection

Proceedings of the 10th Workshop on Optimizations for DSP and Embedded Systems

Thermal-aware datapath merging for coarse-grained reconfigurable processors

Proceedings of the Conference on Design, Automation and Test in Europe

A novel framework for applying multiobjective GA and PSO based approaches for simultaneous area, delay, and power optimization in high level synthesis of datapaths

VLSI Design - Special issue on New Algorithmic Techniques for Complex EDA Problems

HLS-dv: a high-level synthesis framework for dual-Vdd architectures

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Register allocation for embedded systems to simultaneously reduce energy and temperature on registers

ACM Transactions on Embedded Computing Systems (TECS)