Simultaneous functional-unit binding and floorplanning
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Register allocation and binding for low power
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Module assignment for low power
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Resource sharing in hierarchical synthesis
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Improved interconnect sharing by identity operation insertion
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Estimation of lower and upper bounds on the power consumption from scheduled data flow graphs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
A super-scheduler for embedded reconfigurable systems
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Approximating Maximum Independent Sets by Excluding Subgraphs
SWAT '90 Proceedings of the 2nd Scandinavian Workshop on Algorithm Theory
Predictability: definition, ananlysis and optimization
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Wire routing by optimizing channel assignment within large apertures
DAC '71 Proceedings of the 8th Design Automation Workshop
Approximations of weighted independent set and hereditary subset problems
COCOON'99 Proceedings of the 5th annual international conference on Computing and combinatorics
FPGA-targeted high-level binding algorithm for power and area reduction with glitch-estimation
Proceedings of the 46th Annual Design Automation Conference
VLSI Design - Special issue on New Algorithmic Techniques for Complex EDA Problems
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This article proposes two very fast graph theoretic heuristics for the low power binding problem given fixed number of resources and multiple architectures for the resources. First, the generalized low power binding problem is formulated as an Integer Linear Programming (ILP) problem that happens to be an NP-complete task to solve. Then two polynomial-time heuristics are proposed that provide a speedup of up to 13.7 with an extremely low penalty for power when compared to the optimal ILP solution for our selected benchmarks.