Allocation algorithms based on path analysis
Integration, the VLSI Journal - Special issue on high-level synthesis
High-level synthesis in an industrial environment
IBM Journal of Research and Development - Special issue: IBM CMOS technology
False loops through resource sharing
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
A method of automatic data path synthesis
DAC '83 Proceedings of the 20th Design Automation Conference
The development of a high-level synthesis system for concurrent vlsi systems
The development of a high-level synthesis system for concurrent vlsi systems
Redesign using state splitting
EURO-DAC '90 Proceedings of the conference on European design automation
Quadratic zero-one programming-based synthesis of application-specific data paths
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An algorithm to determine mutually exclusive operations in behavioral descriptions
Proceedings of the conference on Design, automation and test in Europe
Global resource sharing for synthesis of control data flow graphs on FPGAs
Proceedings of the 40th annual Design Automation Conference
Register binding and port assignment for multiplexer optimization
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Applying Resource Sharing Algorithms to ADL-driven Automatic ASIP Implementation
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Combining module selection and resource sharing for efficient FPGA pipeline synthesis
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
Resource sharing in pipelined CDFG synthesis
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Effective techniques for the generalized low-power binding problem
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Automatic application specific floating-point unit generation
Proceedings of the conference on Design, automation and test in Europe
Rapid application specific floating-point unit generation with bit-alignment
Proceedings of the 45th annual Design Automation Conference
Area optimisation for field-programmable gate arrays in SystemC hardware compilation
International Journal of Reconfigurable Computing - Selected Papers from SPL 2008: Programmable Logic and Applications
Custom floating-point unit generation for embedded systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Resource sharing is one of the main tasks in high-level synthesis, and although many algorithms have addressed the problem there are still several limitations which restrict the generality and applicability of current algorithms. Most clique-partitioning-based algorithms use local and inaccurate cost-functions which result in inefficient results. This paper presents algorithms for the resource sharing problem on registers and functional units, and shows how they overcome the limitations of existing algorithms. The main characteristics of this work are: interleaved register and functional unit merging in a global clique partitioning based framework, accurate merging cost estimation, accurate interconnect cost estimation, relative control cost taken into account and efficient false loop elimination. The results obtained show significant improvements in the delay of designs, while also minimizing area, specially for large designs with many sharing possibilities.