Predicting area-time tradeoffs for pipelined design
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Behavior-preserving transformations for high-level synthesis
Proceedings of the Mathematical Sciences Institute workshop on Hardware specification, verification and synthesis: mathematical aspects
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
A method of automatic data path synthesis
DAC '83 Proceedings of the 20th Design Automation Conference
Automated exploration of the design space for register-transfer (rt) systems.
Automated exploration of the design space for register-transfer (rt) systems.
Data-path synthesis using path analysis
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
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In high-level synthesis, the generation of different designs is generally referred to as design space exploration. This paper presents an efficient and accurate method for design space exploration based on redesign. Initially, a design that optimizes a design criterion such as performance is synthesized. State splitting them successively generates new designs by introducing additional control states. The size of each design is accurately estimated using a tentative data-path allocation and then computing its area using a typical CMOS cell library implementation. Results for six benchmark examples illustrate these techniques.