The ADAM advanced design automation system: overview, planner and natural language interface
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Sehwa: a program for synthesis of pipelines
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
PLEST: a program for area estimation of VLSI integrated circuits
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Experience with ADAM synthesis system
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Timing models for high-level synthesis
EURO-DAC '92 Proceedings of the conference on European design automation
Design exploration for high-performance pipelines
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Automatic synthesis of pipeline structures with variable data initiation intervals
DAC '94 Proceedings of the 31st annual Design Automation Conference
False path exclusion in delay analysis of RTL-based datapath-controller designs
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Module selection for pipelined synthesis
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
False path exclusion in delay analysis of RTL structures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Heuristic for Clock Selection in High-Level Synthesis
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Redesign using state splitting
EURO-DAC '90 Proceedings of the conference on European design automation
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In this paper we give a model for predicting the shape of cost-speed tradeoff curves for pipelined designs. The model includes prediction of the number of operators, registers and multiplexers from a behavioral specification. It has been verified with the designs generated by an automated pipeline synthesis program, Sehwa. This model was developed as a part of the ADAM Advanced Design Automation System of the University of Southern California.