Predicting area-time tradeoffs for pipelined design
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Tutorial on high-level synthesis
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Module selection for pipelined synthesis
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
MAHA: a program for datapath synthesis
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Representing conditional branches for high-level synthesis applications
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
An intelligent component database for behavioral synthesis
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Data path tradeoffs using MABAL
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
High-level synthesis: technology transfer to industry
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Automatic Synthesis of SARA Design Models from System Requirements
IEEE Transactions on Software Engineering
CHOP: A constraint-driven system-level partitioner
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
The effects of physical design characteristics on the area-performance tradeoff curve
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Empirical evaluation of some high-level synthesis scheduling heuristics
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
SYNTEST: an environment for system-level design for test
EURO-DAC '92 Proceedings of the conference on European design automation
Design assistance for CAD frameworks
EURO-DAC '92 Proceedings of the conference on European design automation
DAC '93 Proceedings of the 30th international Design Automation Conference
A recursive technique for computing lower-bound performance of schedules
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Timing estimation for behavioral descriptions
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
An improved method for RTL synthesis with testability tradeoffs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Reconfigurable scan chains: a novel approach to reduce test application time
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Behavior tables: a basis for system representation and transformational system synthesis
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Improving Testability of Non-Scan Designs during BehavioralSynthesis
Journal of Electronic Testing: Theory and Applications - Special issue on test synthesis
Estimation of lower bounds in scheduling algorithms for high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Accurate layout area and delay modeling for system level design
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
BISTing Datapaths under Heterogeneous Test Schemes
Journal of Electronic Testing: Theory and Applications - Special issue on the IEEE European Test Workshop
Lower bound on latency for VLIW ASIP datapaths
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Lower bound on latency for VLIW ASIP datapaths
Readings in hardware/software co-design
High-level synthesis for easy testability
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Analyzing Testability from Behavioral to RT Level
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Open-ended system for high-level synthesis of flexible signal processors
EURO-DAC '90 Proceedings of the conference on European design automation
Optimal and heuristic algorithms for solving the binding problem
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The ADAM synthesis system consists of two major subsystems: the program tools which synthesize RTL designs from behavioral descriptions and the prediction tools which guide the designer in exploring the design space for a good design. In this paper, we demonstrate the necessity for predictions in narrowing the search space. With the aid of an example, we describe the interaction of a designer with the two subsystems in designing an RTL implementation which maximizes performance while meeting a given area constraint.