Scheduling and binding algorithms for high-level synthesis
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Experience with ADAM synthesis system
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Accumulator-Based Compaction of Test Responses
IEEE Transactions on Computers
Test pattern generation based on arithmetic operations
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
BIST Pattern Generators Using Addition and Subtraction Operations
Journal of Electronic Testing: Theory and Applications - Special issue on test synthesis
Testability analysis and insertion for RTL circuits based on pseudorandom BIST
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Test Synthesis in the Behavioral Domain
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
An Effective BIST Scheme for Booth Multipliers
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Allocation and Assignment in High-Level Synthesis for Self-Testable Data Paths
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
An Effective BIST Scheme for Datapaths
Proceedings of the IEEE International Test Conference on Test and Design Validity
An effective BIST scheme for carry-save and carry-propagate array multipliers
ATS '95 Proceedings of the 4th Asian Test Symposium
Structural constraints for circular self-test paths
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Arithmetic built-in self test for high-level synthesis
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Testability metrics for synthesis of self-testable designs and effective test plans
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
A Method for Trading off Test Time, Area and Fault Coverage in Datapath BIST Synthesis
Journal of Electronic Testing: Theory and Applications
A Method for Trading off Test Time, Area and Fault Coverage in Datapath BIST Synthesis
ETW '00 Proceedings of the IEEE European Test Workshop
BISTing Data Paths at Behavioral Level
ITC '00 Proceedings of the 2000 IEEE International Test Conference
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In this paper, we present a fast and efficient algorithm for BISTingdatapaths described at the Register Transfer (RT) level. This algorithm isparameterized by user defined tuning factors allowing tradeoffs between faultcoverage, area overhead and test application time. This algorithm is generic in the sense it handle and mixes heterogeneous test pattern generators and compactors.