Design of Testable VLSI Circuits with Minimum Area Overhead
IEEE Transactions on Computers
SYNTEST: an environment for system-level design for test
EURO-DAC '92 Proceedings of the conference on European design automation
Accumulator-Based Compaction of Test Responses
IEEE Transactions on Computers
Test pattern generation based on arithmetic operations
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Microarchitectural synthesis of VLSI designs with high test concurrency
DAC '94 Proceedings of the 31st annual Design Automation Conference
Arithmetic Additive Generators of Pseudo-Exhaustive Test Patterns
IEEE Transactions on Computers
Introducing redundant computations in a behavior for reducing BIST resources
DAC '98 Proceedings of the 35th annual Design Automation Conference
A BIST scheme for RTL controller-data paths based on symbolic testability analysis
DAC '98 Proceedings of the 35th annual Design Automation Conference
Allocation Techniques for Reducing BIST Area Overhead ofData Paths
Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
High-Level Test Synthesis for Behavioral and Structural Designs
Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
Efficient BIST hardware insertion with low test application time for synthesized data paths
DATE '99 Proceedings of the conference on Design, automation and test in Europe
BISTing Datapaths under Heterogeneous Test Schemes
Journal of Electronic Testing: Theory and Applications - Special issue on the IEEE European Test Workshop
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Proceedings of the conference on Design, automation and test in Europe
SYNCBIST: SYNthesis for Concurrent Built-In-Self-Testability
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Allocation and Assignment in High-Level Synthesis for Self-Testable Data Paths
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
An Effective BIST Scheme for Datapaths
Proceedings of the IEEE International Test Conference on Test and Design Validity
Structural BIST Insertion Using Behavioral Test Analysis
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Hardware-optimal test register insertion
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Method for Trading off Test Time, Area and Fault Coverage in Datapath BIST Synthesis
Journal of Electronic Testing: Theory and Applications
A Method for Trading off Test Time, Area and Fault Coverage in Datapath BIST Synthesis
ETW '00 Proceedings of the IEEE European Test Workshop
Datapath BIST Insertion Using Pre-Characterized Area and Testability Data
Journal of Electronic Testing: Theory and Applications
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This paper presents a method for deriving a BISTspecification directly from the initial specification ofdatapath architectures. It minimizes BIST area overheadwhile guaranteeing user chosen fault coverage. Theresults show great improvements over lower leveltechniques.