A data path synthesis method for self-testable designs
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Microarchitectural synthesis of VLSI designs with high test concurrency
DAC '94 Proceedings of the 31st annual Design Automation Conference
Data path allocation for synthesizing RTL design with low BIST area overhead
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Lower bounds on test resources for scheduled data flow graphs
DAC '96 Proceedings of the 33rd annual Design Automation Conference
An improved method for RTL synthesis with testability tradeoffs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Allocation and Assignment in High-Level Synthesis for Self-Testable Data Paths
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
A Synthesis-for-Test Design System
A Synthesis-for-Test Design System
Introducing redundant computations in a behavior for reducing BIST resources
DAC '98 Proceedings of the 35th annual Design Automation Conference
Allocation Techniques for Reducing BIST Area Overhead ofData Paths
Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
Estimation of BIST Resources During High-Level Synthesis
Journal of Electronic Testing: Theory and Applications
Introducing redundant computations in RTL data paths for reducing BIST resources
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Test session oriented built-in self-testable data path synthesis
ITC '98 Proceedings of the 1998 IEEE International Test Conference
BISTing Data Paths at Behavioral Level
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Concurrent BIST synthesis and test scheduling using genetic algorithms
International Journal of Computers and Applications
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Built-in self-test (BIST) techniques modify functional hardware to give a data path the capability to test itself. The modification of data path registers into registers (BIST resources) that can generate pseudo-random test patterns and/or compress test responses, incurs an area overhead penalty. We show how scheduling and module assignment in high-level synthesis affect BIST resource requirements of a data path. A scheduling and module assignment procedure is presented that produces schedules which, when used to synthesize data paths, result in a significant reduction in BIST area overhead and hence total area.