Estimation of BIST Resources During High-Level Synthesis

  • Authors:
  • Ishwar Parulkar;Sandeep K. Gupta;Melvin A. Breuer

  • Affiliations:
  • Sun Microsystems, Inc., Palo Alto, CA 94303. ishwar.parulkar@sun.com;Department of Electrical Engineering—Systems, University of Southern California, Los Angeles, CA 90089. sandeep@poisson.usc.edu;Department of Electrical Engineering—Systems, University of Southern California, Los Angeles, CA 90089. mb@poisson.usc.edu

  • Venue:
  • Journal of Electronic Testing: Theory and Applications
  • Year:
  • 1998

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Abstract

A general method for determining whether a certain design is initializable, and for generating its initialization sequence, is presented in this paper. This method is based on structural decomposition of the circuit, and can handle both logical ...