Optimization of bist resources during high-level synthesis

Allocation Techniques for Reducing BIST Area Overhead ofData Paths

Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis

Estimation of BIST Resources During High-Level Synthesis

Journal of Electronic Testing: Theory and Applications

Introducing redundant computations in RTL data paths for reducing BIST resources

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Keynote speech: testing methodologies for embedded systems and systems-on-chip

ICESS'04 Proceedings of the First international conference on Embedded Software and Systems