Test Scheduling and Control for VLSI Built-in Self-Test
IEEE Transactions on Computers
Design of Testable VLSI Circuits with Minimum Area Overhead
IEEE Transactions on Computers
A data path synthesis method for self-testable designs
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Microarchitectural synthesis of VLSI designs with high test concurrency
DAC '94 Proceedings of the 31st annual Design Automation Conference
An improved method for RTL synthesis with testability tradeoffs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Introducing redundant computations in a behavior for reducing BIST resources
DAC '98 Proceedings of the 35th annual Design Automation Conference
Scheduling and module assignment for reducing BIST resources
Proceedings of the conference on Design, automation and test in Europe
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
The Synthesis Approach to Digital System Design
The Synthesis Approach to Digital System Design
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
SYNCBIST: SYNthesis for Concurrent Built-In-Self-Testability
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Allocation and Assignment in High-Level Synthesis for Self-Testable Data Paths
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Synthesizing for Scan Dependence in Built-In Self-Testable Designs
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Arithmetic built-in self test for high-level synthesis
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
A Synthesis-for-Test Design System
A Synthesis-for-Test Design System
Optimization of bist resources during high-level synthesis
Optimization of bist resources during high-level synthesis
Algorithmic Graph Theory and Perfect Graphs (Annals of Discrete Mathematics, Vol 57)
Algorithmic Graph Theory and Perfect Graphs (Annals of Discrete Mathematics, Vol 57)
Microarchitectural synthesis for rapid BIST testing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Introducing redundant computations in RTL data paths for reducing BIST resources
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A Method for Trading off Test Time, Area and Fault Coverage in Datapath BIST Synthesis
Journal of Electronic Testing: Theory and Applications
A Method for Trading off Test Time, Area and Fault Coverage in Datapath BIST Synthesis
ETW '00 Proceedings of the IEEE European Test Workshop
BISTing Data Paths at Behavioral Level
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Concurrent BIST synthesis and test scheduling using genetic algorithms
International Journal of Computers and Applications
| Hi-index | 0.01 |
Built-in self-test (BIST) techniques modify functional hardware so that a chip has the capability to test itself. A prime concern in using BIST is the area overhead due to the modification of normal registers to BIST registers. This paper proposes registerand interconnect assignment techniques that address the BIST area overheadissue during high-level synthesis. A minimal intrusion BISTmethodology is employed where a subset of the functional registers aremodified to be BIST registers. Depending on the BIST functionsperformed (test pattern generation and/or test response compression) and the concurrency of the functions, four types of BIST registers with varying costs are used. Data path allocation techniques are presented that (1) maximize the sharing of BIST registersbetween modules, and (2) minimize the number of expensive BISTregisters that are essential for minimal intrusion BIST of adata path. The designs synthesized by our techniques have the same number of functional modules and registers as thosesynthesized using traditional approaches but require significantlylower BIST area overhead.