RTL Test Justification and Propagation Analysis for Modular Designs
Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
Allocation Techniques for Reducing BIST Area Overhead ofData Paths
Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
Channel-based behavioral test synthesis for improved module reachability
DATE '99 Proceedings of the conference on Design, automation and test in Europe
On ILP formulations for built-in self-testable data path synthesis
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Test session oriented built-in self-testable data path synthesis
ITC '98 Proceedings of the 1998 IEEE International Test Conference
DFT guidance through RTL test justification and propagation analysis
ITC '98 Proceedings of the 1998 IEEE International Test Conference
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Datapath BIST Insertion Using Pre-Characterized Area and Testability Data
Journal of Electronic Testing: Theory and Applications
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The impact of testability on design cost necessitates its consideration during the earliest stages of synthesis. Built-in self test (BIST) is an accepted testing approach, but its application to many designs is limited by the long test application time required to achieve high fault coverage. This work addresses the problem of BIST test time for high fault coverage by targeting test concurrency during high-level and structural synthesis. High-level synthesis generates RTL circuits which guarantee concurrent controllability and observability of all hardware components from test registers. Structural synthesis for testability completes the microarchitectural definition by specifying the test registers in the circuit, and defining a BIST test plan for the circuit. Remaining test conflicts are avoided without reducing test throughput by using partial-intrusion BIST to enable test data to be pipelined through nontest registers. The use of pipelined BIST testing in conjunction with high-level synthesis for test conflict minimization enables reduced test time through high test concurrency. Partial-intrusion BIST reduces the number of test registers by using nontest registers to propagate test data. Both behavioral and structural synthesis are directed by testability metrics which measure the test concurrency of a design. The use of these metrics in an integrated behavioral synthesis system pioneers the inclusion of test concurrency issues in microarchitectural synthesis. Experimental results using this synthesis system, SYNCBIST, show that designs generated by this approach are testable with few patterns, and using few test registers