Proofs: a fast, memory efficient sequential circuit fault simulator
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Automatic test knowledge extraction from VHDL (ATKET)
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
A design for testability technique for RTL circuits using control/data flow extraction
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
The Designer's Guide to VHDL
Computer Architecture and Organization
Computer Architecture and Organization
Test Propagation Through Modules and Circuits
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
A Novel Functional Test Generation Method for Processors Using Commercial ATPG
Proceedings of the IEEE International Test Conference
Modifying User-Defined Logic for Test Access to Embedded Cores
Proceedings of the IEEE International Test Conference
A Low-Overhead Design for Testability and Test Generation Technique for Core-Based Systems
Proceedings of the IEEE International Test Conference
Testability Analysis and ATPG on Behavioral RT-Level VHDL
Proceedings of the IEEE International Test Conference
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
Microarchitectural synthesis for rapid BIST testing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast Hierarchical Test Path Construction for Circuits with DFT-Free Controller-Datapath Interface
Journal of Electronic Testing: Theory and Applications
How to Avoid Random Walks in Hierarchical Test Path Identification
ETW '00 Proceedings of the IEEE European Test Workshop
A synthesis-for-transparency approach for hierarchical and system-on-a-chip test
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We introduce a formal mechanism for capturing testjustification and propagation related behavior of blocks.Based on the identified test translation behavior, an RTLtestability analysis methodology for hierarchical designs isderived. An algorithm for pinpointing the local-to-globaltest translation controllability and observabilitybottlenecks is presented. The analysis results are validatedthrough an ATPG-based experimental flow and theapplicability of the scheme for addressing test challengesin large designs by guiding DFT decisions is discussed.