Proofs: a fast, memory efficient sequential circuit fault simulator
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Automatic test knowledge extraction from VHDL (ATKET)
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Enhancing high-level control-flow for improved testability
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Behavioral Testability Insertion for Datapath/Controller Circuits
Journal of Electronic Testing: Theory and Applications - Special issue on test synthesis
RTL Test Justification and Propagation Analysis for Modular Designs
Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
The Designer's Guide to VHDL
Computer Architecture and Organization
Computer Architecture and Organization
Test Propagation Through Modules and Circuits
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
A Novel Functional Test Generation Method for Processors Using Commercial ATPG
Proceedings of the IEEE International Test Conference
DFT guidance through RTL test justification and propagation analysis
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Testing embedded-core based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
CHEETA: Composition of Hierarchical Sequential Tests Using ATKET
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
HOPE: an efficient parallel fault simulator for synchronous sequential circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hierarchical test generation under architectural level functional constraints
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A controller redesign technique to enhance testability of controller-data path circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Low test application time resource binding for behavioral synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Hierarchical approaches address the complexity of test generation through symbolic reachability paths that provide access to the I/Os of each module in a design. However, while transparency behavior suitable for symbolic design traversal can be utilized for constructing reachability paths for datapath modules, control modules do not exhibit transparency. Therefore, incorporating such modules in reachability path construction requires exhaustive search algorithms or expensive DFT hardware. In this paper, we discuss a fast hierarchical test path construction method for circuits with DFT-free controller-datapath interface. A transparency-based RT-Level hierarchical test generation scheme is devised for the datapath, wherein locally generated vectors are translated into global design test. Additionally, the controller is examined through the introduced concept of influence tables, which are used to generate valid control state sequences for testing each module through hierarchical test paths. Fault coverage and vector count levels thus attained match closely those of traditional test generation methods, while sharply reducing the corresponding computational cost and test generation time.