Computer architecture and organization; (2nd ed.)
Computer architecture and organization; (2nd ed.)
Proofs: a fast, memory efficient sequential circuit fault simulator
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Automatic test knowledge extraction from VHDL (ATKET)
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Automatic functional test generation using the extended finite state machine model
DAC '93 Proceedings of the 30th international Design Automation Conference
A design for testability technique for RTL circuits using control/data flow extraction
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
The Designer's Guide to VHDL
A Unified Framework for Design Validation and Manufacturing Test
Proceedings of the IEEE International Test Conference on Test and Design Validity
Test Propagation Through Modules and Circuits
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
A Novel Functional Test Generation Method for Processors Using Commercial ATPG
Proceedings of the IEEE International Test Conference
Modifying User-Defined Logic for Test Access to Embedded Cores
Proceedings of the IEEE International Test Conference
A Low-Overhead Design for Testability and Test Generation Technique for Core-Based Systems
Proceedings of the IEEE International Test Conference
High-Level Test Generation Using Symbolic Scheduling
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Testability Analysis and ATPG on Behavioral RT-Level VHDL
Proceedings of the IEEE International Test Conference
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
Microarchitectural synthesis for rapid BIST testing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Channel-based behavioral test synthesis for improved module reachability
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Fast Hierarchical Test Path Construction for Circuits with DFT-Free Controller-Datapath Interface
Journal of Electronic Testing: Theory and Applications
Statistical Tolerance Analysis for Assured Analog Test Coverage
Journal of Electronic Testing: Theory and Applications
How to Avoid Random Walks in Hierarchical Test Path Identification
ETW '00 Proceedings of the IEEE European Test Workshop
A synthesis-for-transparency approach for hierarchical and system-on-a-chip test
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Searching for Global Test Costs Optimization in Core-Based Systems
Journal of Electronic Testing: Theory and Applications
On the identification of modular test requirements for low cost hierarchical test path construction
Integration, the VLSI Journal
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Modular decomposition and functional abstraction arecommonly employed to accommodate the growing size and complexity ofmodern designs. In the test domain, a divide-and-conquertype of approach is utilized, wherein test is locally generated for each module and consequently translated to globaldesign test. We present an RTL analysis methodology thatidentifies the test justification and propagation bottlenecks,facilitating a judicious DFT insertion process. We introducetwo mechanisms for capturing, without reasoning on thecomplete functional space, data and control module behaviorrelated to test translation. A traversal algorithm thatidentifies the test translation bottlenecks in the design isdescribed. The algorithm is capable of handling cyclicbehavior, reconvergence and variable bit-widths in anefficient manner. We demonstrate our scheme on representativeexamples, unveiling its potential of accurately identifyingand consequently minimizing the reported controllability andobservability bottlenecks of large, modular designs.