RTL Test Justification and Propagation Analysis for Modular Designs
Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
Test Selection Based on High Level Fault Simulation for Mixed-Signal Systems
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Hierarchical test generation under architectural level functional constraints
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Worst case tolerance analysis and CLP-based multifrequency test generation for analog circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design of concurrent test hardware for linear analog circuits with constrained hardware overhead
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hierarchical analysis of process variation for mixed-signal systems
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
| Hi-index | 0.00 |
Increasing numbers of analog components in today's systems necessitate system level test composition methods that utilize on-chip capabilities rather than solely relying on costly DFT approaches. We outline a tolerance analysis methodology for test signal propagation to be utilized in hierarchical test generation for analog circuits. A detailed justification of this proposed novel tolerance analysis methodology is undertaken by comparing our results with detailed SPICE Monte-Carlo simulation data on several combinations of analog modules. The results of our experiments confirm the high accuracy and efficiency of the proposed tolerance analysis methodology.