Scalable Test Generators for High-Speed Datapath Circuits
Journal of Electronic Testing: Theory and Applications - Special issue on On-line testing
RTL Test Justification and Propagation Analysis for Modular Designs
Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
Test generation for Gigahertz processors using an automatic functional constraint extractor
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
An Effective Built-In Self-Test Scheme for Parallel Multipliers
IEEE Transactions on Computers
Computer arithmetic: algorithms and hardware designs
Computer arithmetic: algorithms and hardware designs
The Designer's Guide to VHDL
On IEEE P1500's Standard for Embedded Core Test
Journal of Electronic Testing: Theory and Applications
R-CBIST: an effective RAM-based input vector monitoring concurrent BIST technique
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Testing embedded-core based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
CHEETA: Composition of Hierarchical Sequential Tests Using ATKET
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Efficient Transparency Extraction and Utilization in Hierarchical Test
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
A Knowledge-Based System for Designing Testable VLSI Chips
IEEE Design & Test
Design of Easily Testable Bit-Sliced Systems
IEEE Transactions on Computers
IEEE Transactions on Computers
IEEE Transactions on Computers
Hierarchical test generation under architectural level functional constraints
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hierarchical test generation using precomputed tests for modules
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
C-Testability of Two-Dimensional Iterative Arrays
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A concurrent testing technique for digital circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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We discuss a novel method for identifying test requirements of modules in a hierarchical design in order to facilitate the construction of cost-effective hierarchical test paths. Unlike current practices, which construct very general paths capable of justifying all vectors and propagating all responses to and from each module in the design, test requirements in our method are defined as a set of fine-grained input and output bit clusters and pertinent symbolic values. These test requirements reflect the inherent connectivity and regularity of each module and, when supported by corresponding hierarchical test paths, they guarantee complete testability of the module. Their key advantage is that they are not fully specified test vectors and, therefore, they do not require a computationally expensive search algorithm to satisfy from the primary inputs and outputs of the circuit. At the same time, they are also not arbitrarily general and, therefore, they do not impose overly strenuous transparency requirements on the surrounding modules, which could require excessive design-for-testability hardware. In essence, they combine the generality required for fast hierarchical test path construction with the precision necessary for minimizing the incurred cost, thus fostering cost-effective hierarchical test.