A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
Test generation for large logic networks
DAC '77 Proceedings of the 14th Design Automation Conference
Enhancing Testability of Large-Scale Integrated Circuits via Test Points and Additional Logic
IEEE Transactions on Computers
An Advanced Fault Isolation System for Digital Logic
IEEE Transactions on Computers
Syndrome-Testable Design of Combinational Circuits
IEEE Transactions on Computers
Measures of the Effectiveness of Fault Signature Analysis
IEEE Transactions on Computers
Testable Realizations for FET Stuck-Open Faults in CMOS Combinational Logic Circuits
IEEE Transactions on Computers
Test Length for Pseudorandom Testing
IEEE Transactions on Computers
A tree-structured LFSR synthesis scheme for pseudo-exhaustive testing of VLSI circuits
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Detection of CMOS address decoder open faults with March and pseudo random memory tests
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Integration of Non-Classical Faults in Standard March Tests
MTDT '98 Proceedings of the 1998 IEEE International Workshop on Memory Technology, Design and Testing
Incorporating Physical Design-For-Test Into Routing
ITC '97 Proceedings of the 1997 IEEE International Test Conference
On the identification of modular test requirements for low cost hierarchical test path construction
Integration, the VLSI Journal
Verification Testing A Pseudoexhaustive Test Technique
IEEE Transactions on Computers
Logic Test Pattern Generation Using Linear Codes
IEEE Transactions on Computers
Exhaustive Test Pattern Generation with Constant Weight Vectors
IEEE Transactions on Computers
Iterative exhaustive pattern generation for logic testing
IBM Journal of Research and Development
Reconfigurable hardware for Pseudo-exhaustive test
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
On the testing of multiplexers
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Design for testability of mixed signal integrated circuits
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Partial hardware partitioning: a new pseudo-exhaustive test implementation
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
IEEE Transactions on Computers
An analysis of the multiple fault detection capabilities of single stuck-at fault test sets
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
Can we eliminate fault escape in self testing by polynomial division (signature analysis)?
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
Pseudo-exhaustive testing of sequential machines using signature analysis
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
A built-in test methodology for VLSI data paths
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
On methods to match a test pattern generator to a circuit-under-test
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
AsiaSim'04 Proceedings of the Third Asian simulation conference on Systems Modeling and Simulation: theory and applications
| Hi-index | 15.00 |
A technique for modifying networks so that they are capable of self test is presented. The major innovation is partitioning the network into subnetworks with sufficiently few inputs that exhaustive testing of the subnetworks is possible.