Logic design principles with emphasis on testable semicustom circuits
Logic design principles with emphasis on testable semicustom circuits
IEEE Transactions on Computers
Probabilistic Treatment of General Combinational Networks
IEEE Transactions on Computers
About Random Fault Detection of Combinational Networks
IEEE Transactions on Computers
IEEE Transactions on Computers
IEEE Transactions on Computers
Random-pattern coverage enhancement and diagnosis for LSSD logic self-test
IBM Journal of Research and Development
IEEE Transactions on Computers
A method for generating weighted random test pattern
IBM Journal of Research and Development
On Computing Signal Probability and Detection Probability of Stuck-At Faults
IEEE Transactions on Computers
IEEE Transactions on Computers
Test-Pattern Generation Based on Reed-Muller Coefficients
IEEE Transactions on Computers
A programmable multiple-sequence generator for BIST applications
ATS '95 Proceedings of the 4th Asian Test Symposium
Minimal length test vectors for multiple-fault detection
Theoretical Computer Science - Mathematical foundations of programming semantics
Evaluation of system BIST using computational performance measures
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
| Hi-index | 14.99 |
The process of determining the required test length for a desired level of confidence for pseudorandom testing using a random sampling without replacement model is examined. The differences between random and pseudorandom testing are discussed and developed. The strictly random testing model is shown to be inaccurate for high confidence testing of combinational circuits. A method of calculating the required test length for pseudorandom testing based upon fault detectabilities is described. The result provides a very accurate prediction of required test length applicable to self-test using pseudorandom inputs.