Data structures and network algorithms
Data structures and network algorithms
The design and analysis of VLSI circuits
The design and analysis of VLSI circuits
Partitioning circuits for inproved testability
Proceedings of the fourth MIT conference on Advanced research in VLSI
Test Length for Pseudorandom Testing
IEEE Transactions on Computers
Computer-aided verification of coordinating processes: the automata-theoretic approach
Computer-aided verification of coordinating processes: the automata-theoretic approach
An Efficient Implementation of Edmonds' Algorithm for Maximum Matching on Graphs
Journal of the ACM (JACM)
On the complexity of edge traversing
Journal of the ACM (JACM)
SIFA: a tool for evaluation of high-grade security devices
ACISP'05 Proceedings of the 10th Australasian conference on Information Security and Privacy
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A methodology for circuit testing is proposed for detecting multiple circuit faults in the course of a minimal length "guided tour" of the circuit transition structure. Deriving a test vector to guide this tour through an n state subsystem with at most I inputs possible in situ at each state, corresponds to solving an open tour multigraph version of the "Chinese Postman" problem, in which out-degrees are bounded by I. In this case, the length L of a minimal length open tour is shown to satisfy L ≤ In2; a minimal length open tour is computable in O(n3 + nI) steps for undirected multigraphs and O(n3 + (nI)2logn/logI) steps for directed multigraphs, both one-time costs, using weighted matching and bipartite weighted matching, respectively. An open tour can result in a test vector as much as ½ shorter than the test vector associated with a closed tour, without any loss in error detection. Examples show that for a directed graph, the length of a minimal length open tour may be as great as n3/6 for I = n, or Ω(n2) when I is bounded, while in an undirected multigraph, a minimal length tour requires no more than n - 3 repeated state transitions. This mitigates in favor of "mixed" circuits in which certain transitions are reversible and need be tested in only one direction.The practicality of this approach rests with the ability to apply it separately to small sub-systems, in conjunction with symbolic testing of inter-subsystem coordination. The former is feasible with existing commercial technologies, such as electron beam scanning, while the latter is feasible with a finite-state model-checker.In summary, the proposed methodology comprises three steps: 1. decompose a circuit into subsystems sufficiently small to be model-checked exhaustively; 2. perform symbolic tests of inter-subsystem coordination and conclude that if each subsystem is correctly implemented, then the entire circuit will behave as required; 3. for each circuit subsystem, exercise every realizable transition through a minimal length (open) tour, comparing the actual transitions with those of the specification.