IEEE Transactions on Computers
Test Length for Pseudorandom Testing
IEEE Transactions on Computers
Fault Detection in Combinational Networks by Reed-Muller Transforms
IEEE Transactions on Computers
Spectral Techniques and Fault Detection
Spectral Techniques and Fault Detection
Spectral Techniques in Digital Logic
Spectral Techniques in Digital Logic
Optimization Problems on Concurrent Testing Solved by Neural Networks
IWANN '91 Proceedings of the International Workshop on Artificial Neural Networks
Test generation costs analysis and projections
DAC '80 Proceedings of the 17th Design Automation Conference
Performance Testing a Large Finance Application
IEEE Software
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Reed-Muller coefficients are used to generate a test-pattern selection procedure for detecting single stuck-at faults. This procedure is based on the heuristics deduced from the way in which the spectral coefficients are affected by such faults. The changes that the spectral coefficients undergo are also compared with the fault models used most frequently to model defects in combinational circuits. The proposed pattern-generating procedure does not need a simulation of the circuit for each of the possible stuck-at faults, and its complexity is proportional to the number of gates in the circuit. The proportionality constant increases exponentially as the number of inputs in the circuit increases. To evaluate the performance of the proposed method, its application to some benchmark circuits, including the ALU 74181, is presented.