Test Length for Pseudorandom Testing
IEEE Transactions on Computers
On computing optimized input probabilities for random tests
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
PROTEST: a tool for probabilistic testability analysis
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
DAC '84 Proceedings of the 21st Design Automation Conference
Test generation costs analysis and projections
DAC '80 Proceedings of the 17th Design Automation Conference
An automated method for designing logic circuit diagnostic programs
DAC '71 Proceedings of the 8th Design Automation Workshop
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
An Advanced Fault Isolation System for Digital Logic
IEEE Transactions on Computers
IEEE Transactions on Computers
Probabilistic Treatment of General Combinational Networks
IEEE Transactions on Computers
The Weighted Random Test-Pattern Generator
IEEE Transactions on Computers
Test Length in a Self-Testing Environment
IEEE Design & Test
The development of ultra-high-frequency VLSI device test systems
IBM Journal of Research and Development
A logic chip delay-test method based on system timing
IBM Journal of Research and Development
An ac test structure for fast memory arrays
IBM Journal of Research and Development
Boundary-scan design principles for efficient LSSD ASIC testing
IBM Journal of Research and Development
IBM Journal of Research and Development
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Test pattern generation hardware motivated by pseudo-exhaustive test techniques
EURO-DAC '94 Proceedings of the conference on European design automation
On Evaluating and Optimizing Weights for Weighted Random Pattern Testing
IEEE Transactions on Computers
Test methodologies and design automation for IBM ASICs
IBM Journal of Research and Development
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Efficient random testing with global weights
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
STARBIST: scan autocorrelated random pattern generation
DAC '97 Proceedings of the 34th annual Design Automation Conference
Cellular Automata for Weighted Random Pattern Generation
IEEE Transactions on Computers
Advanced microprocessor test strategy and methodology
IBM Journal of Research and Development - Special issue: IBM S/390 G3 and G4
Synthesis of BIST hardware for performance testing of MCM interconnections
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Distributed Generation of Weighted Random Patterns
IEEE Transactions on Computers
Testability of 2-Level AND/EXOR Circuits
Journal of Electronic Testing: Theory and Applications
Application of Deterministic Logic BIST on Industrial Circuits
Journal of Electronic Testing: Theory and Applications
On-the-Fly Reseeding: A New Reseeding Technique for Test-Per-Clock BIST
Journal of Electronic Testing: Theory and Applications
Failure Diagnosis of Structured VLSI
IEEE Design & Test
Low-Cost Testing of High-Density Logic Components
IEEE Design & Test
A Tutorial on Built-In Self-Test, Part 2: Applications
IEEE Design & Test
Testing the 500-MHz IBM S/390 Microprocessor
IEEE Design & Test
ATPG in practical and non-traditional applications
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Microprocessor test and test tool methodology for the 500 MHz IBM S/390 G5 chip
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Deterministic Pattern Generation for Weighted Random Pattern Testing
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Testability of 2-level AND/EXOR circuits
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Methods to reduce test application time for accumulator-based self-test
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
On Optimizing BIST-Architecture by Using OBDD-based Approaches and Genetic Algorithms
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Instruction Randomization Self Test For Processor Cores
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Non-Intrusive BIST for Systems-on-a-Chip
ITC '00 Proceedings of the 2000 IEEE International Test Conference
99 % AC test coverage using only LBIST on the 1 GHz IBM S/390 zSeries 900 Microprocessor
ITC '01 Proceedings of the 2001 IEEE International Test Conference
A Building Block BIST Methodology for SOC Designs: A Case Study
ITC '01 Proceedings of the 2001 IEEE International Test Conference
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Low Hardware Overhead Scan Based 3-Weight Weighted Random BIST
ITC '01 Proceedings of the 2001 IEEE International Test Conference
OPMISR: The Foundation for Compressed ATPG Vectors
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Scan Encoded Test Pattern Generation for BIST
ITC '97 Proceedings of the 1997 IEEE International Test Conference
On Using Machine Learning for Logic BIST
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Testing The 400-MHz IBM Generation-4 CMOS Chip
ITC '97 Proceedings of the 1997 IEEE International Test Conference
The effectiveness of different test sets for PLAs
EURO-DAC '90 Proceedings of the conference on European design automation
Logic BIST Using Constrained Scan Cells
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
On High-Quality, Low Energy Built-In Self Test Preparation at RT-Level
Journal of Electronic Testing: Theory and Applications
Hardware Ef.cient LBISTWith Complementary Weights
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
A BIST TPG for low power dissipation and high fault coverage
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
S/390 G5 CMOS microprocessor diagnostics
IBM Journal of Research and Development
Balancing structured and ad-hoc design for test: testing of the PowerPC 603TMmicroprocessor
ITC'94 Proceedings of the 1994 international conference on Test
ASIC test cost/strategy trade-offs
ITC'94 Proceedings of the 1994 international conference on Test
Design of an efficient weighteld random pattern generation system
ITC'94 Proceedings of the 1994 international conference on Test
Weighted pseudorandom hybrid BIST
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An Optimized Seed-based Pseudo-random Test Pattern Generator: Theory and Implementation
Journal of Electronic Testing: Theory and Applications
Increasing embedding probabilities of RPRPs in RIN based BIST
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
LFSR seed computation and reduction using SMT-based fault-chaining
Proceedings of the Conference on Design, Automation and Test in Europe
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