Testing the 500-MHz IBM S/390 Microprocessor

• Authors: Thomas G. Foote;Dale E. Hoffman;William V. Huott;Timothy J. Koprowski;Mary P. Kusko;Bryan J. Robbins
• Venue: IEEE Design & Test
• Year: 1998

This article describes the design-for-test framework of the 500MHz CMOS central processor (CP) used in the IBM Generation-5 S/390 ??line of servers. It will describe details of modeling logic to achieve correct and effective tests as well as describe the test sets required to test all portions of the design. This includes built-in self-test, array self-test, weighted random pattern generation, algorithmic pattern generation, and manual patterns. Tests are used to detect faults, static and dynamic, and to debug/ diagnose chip failures characteristic to the function under test. The described tests ensure the highest reliability for the components within the system. Some of the same test patterns are applied in chip manufacturing and in system level test. The tests developed for the 500MHz chip are very similar to those developed for the 400MHz Generation-4 S/390 chips.The improvements made to the test of the 500MHz chip were to run more patterns, and run them more efficiently in manufacturing. high quality standards but minimize test costs including minimizing dependencies on expensive test equipment. Tester time is minimized with an effective test pattern set while maintaining well over 99% stuck fault test coverage. Extensive testing begins at the wafer level, continues on a temporary single chip carrier, next to the MCM level and finally at the system level. The end result is a thoroughly tested, affordable, and highly diagnosable design.