A method for generating weighted random test pattern
IBM Journal of Research and Development
Chip partitioning aid: A design technique for partitionability and testability in VLSI
DAC '84 Proceedings of the 21st Design Automation Conference
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
Test generation for large logic networks
DAC '77 Proceedings of the 14th Design Automation Conference
DAC '82 Proceedings of the 19th Design Automation Conference
An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
IEEE Transactions on Computers
Self-testing the 16-Mbps adapter chip for the IBM tokenring local area network
IBM Journal of Research and Development
Technology-migratable ASIC library design
IBM Journal of Research and Development
Test methodologies and design automation for IBM ASICs
IBM Journal of Research and Development
A new complete diagnosis patterns for wiring interconnects
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Standard-cell-based design methodology for high-performance support chips
IBM Journal of Research and Development - Special issue: IBM S/390 G3 and G4
Advanced microprocessor test strategy and methodology
IBM Journal of Research and Development - Special issue: IBM S/390 G3 and G4
A new IEEE 1149.1 boundary scan design for the detection of delay defects
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Enhanced Reduced Pin-Count Test for Full-Scan Design
Journal of Electronic Testing: Theory and Applications
Low-Cost Testing of High-Density Logic Components
IEEE Design & Test
Testing the 500-MHz IBM S/390 Microprocessor
IEEE Design & Test
Delay test of chip I/Os using LSSD boundary scan
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Detection of CMOS address decoder open faults with March and pseudo random memory tests
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Microprocessor test and test tool methodology for the 500 MHz IBM S/390 G5 chip
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Integration of Non-Classical Faults in Standard March Tests
MTDT '98 Proceedings of the 1998 IEEE International Workshop on Memory Technology, Design and Testing
Contactless Digital Testing of IC Pin Leakage Currents
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Enhanced Reduced Pin-Count Test for Full-Scan Design
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Testing the Enterprise IBM System/390" Multi Processor
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Testing The 400-MHz IBM Generation-4 CMOS Chip
ITC '97 Proceedings of the 1997 IEEE International Test Conference
ASIC test cost/strategy trade-offs
ITC'94 Proceedings of the 1994 international conference on Test
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