A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
Test generation for large logic networks
DAC '77 Proceedings of the 14th Design Automation Conference
AUTOMATIC SYSTEM LEVEL TEST GENERATION AND FAULT LOCATION FOR LARGE DIGITAL SYSTEMS
DAC '78 Proceedings of the 15th Design Automation Conference
Boundary-scan design principles for efficient LSSD ASIC testing
IBM Journal of Research and Development
A Sweeping Line Approach to Interconnect Testing
IEEE Transactions on Computers
Structural diagnosis of interconnects by coloring
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Chip partitioning aid: A design technique for partitionability and testability in VLSI
DAC '84 Proceedings of the 21st Design Automation Conference
A Low-Cost Massively-Parallel Interconnect Test Method for MCM Substrates
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Modeling for structured system interconnect test
ITC'94 Proceedings of the 1994 international conference on Test
Testing and diagnosis of interconnects using boundary scan architecture
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Scan diagnostic strategy for the series 10000 PRISM workstation
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
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Electronic Chip-in-Place Test (ECIPT) is a design approach and a test methodology for VLSI packages containing multiple semi-conductor chips. Shift register latches are used in such a way that each chip on a package is accessible for testing from the package pins without in-circuit probing. A means is therefore provided, whereby tests generated for a chip can be reapplied at the package level. The ECIPT methodology additionally provides a mechanism for simplified tests of failures associated with interchip wiring and chip I/O connections.