Chip partitioning aid: A design technique for partitionability and testability in VLSI

Authors:
S. DasGupta;M. C. Graf;R. A. Rasmussen;R. G. Walther;T. W. Williams
Affiliations:
IBM Corporation, P.O. Box 390, Poughkeepsie, NY;IBM Corporation, Route 52, Hopewell Junction, NY;IBM Corporation, Route 52, Hopewell Junction, NY;11400 F.M.R.D. 1325, IBM Corporation, Austin, Texas;IBM Corporation, P.O. Box 1900, Boulder, CO
Venue:
DAC '84 Proceedings of the 21st Design Automation Conference
Year:
1984

Citing 5
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IBM Journal of Research and Development

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Abstract

This paper presents a structured partitioning technique which can be integrated into the design of a chip. It breaks the pattern of exponential growth in test pattern generation cost as a function of the number of chips in a package. In one of its forms, it also holds the promise of parallel chip testing, as well as migration of chip-level tests for testing at higher package levels.