Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
DAC '82 Proceedings of the 19th Design Automation Conference
Hi-index | 0.00 |
The series 10000 PRISM Workstation has been designed to be testable using scan path techniques. An overview of the scan architecture at the chip and system levėls shows the basis on which a diagnostic strategy was developed. These strategies were used to achieve diagnostics goals of high fault coverage and component level fault isolation. A unique fault isolation method is described which is based on scan path features of the series 10000 and a logic partitioning method. We will also introduce the software tool set used in scan test development on the series 10000.