The Test Access Port and Boundary-Scan Architecture
The Test Access Port and Boundary-Scan Architecture
IEEE P1149.5 Module Test and Maintenance Bus
IEEE Design & Test
Achieving Board-Level BIST Using the Boundary-Scan Master
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
A Proposed Method of Accessing 1149.1 in a Backplane Environment
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
System Level Interconnect Test in a Tristate Environment
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Hierarchically Accessing 1149.1 Applications in a System Environment
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
A Universal Framework for Managed Built-in Test
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
DAC '82 Proceedings of the 19th Design Automation Conference
Combinatorial Algorithms: Theory and Practice
Combinatorial Algorithms: Theory and Practice
Testing for Faults in Wiring Networks
IEEE Transactions on Computers
Generating interconnect models from prototype hardware
ITC '98 Proceedings of the 1998 IEEE International Test Conference
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With the acceptance of test standards such as IEEE 1149.1, the potential for structured methods for system test is growing rapidly. In particular, interconnect testing based on standardized boundary scan structures will be an important component of a future structured system test methodology. A strategy based on building an interconnect topology model of the system under test and using that model to generate interconnect test patterns at test time provides for a level of system test coverage that is difficult or impossible to obtain from methods based on static stored test patterns. This paper discusses the problem of dynamically generating a model of system interconnect topology for use in structured interconnect test generation and analysis. A solution for the most general case is given and some simple system design for test rules that greatly simplify the process are proposed. Several additional solutions which explore some potential trade-offs are discussed. A practical algorithm that requires minimal storage and reasonable computation is proposed.