Enhanced Reduced Pin-Count Test for Full-Scan Design

Authors:
Harald Vranken;Tom Waayers;Hervé Fleury;David Lelouvier
Affiliations:
Philips Research Laboratories, IC Design—Digital Design & Test, Prof. Holstlaan 4, M/S WAY-41, 5656 AA, Eindhoven, The Netherlands. harald.vranken@philips.com;Philips Research Laboratories, Electronic Design & Tools, Prof. Holstlaan 4, M/S WAY-31, 5656 AA, Eindhoven, The Netherlands. tom.waayers@philips.com;Philips Semiconductors, IC Development—Design for Test, 2, Rue de la Girafe, 14079 Caen Cedex 5, France. herve.fleury@philips.com;Philips Semiconductors, Test & Product Engineering, 2, Rue de la Girafe, 14079 Caen Cedex 5, France. david.lelouvier@philips.com
Venue:
Journal of Electronic Testing: Theory and Applications
Year:
2002

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Abstract

This paper presents enhanced reduced pin-count test (E-RPCT) for low-cost test. E-RPCT is an extension of traditional RPCT for circuits in which a large number of digital IC pins is multiplexed for scan. The basic concept of E-RPCT is to provide access to the internal scan chains via an IEEE 1149.1 compatible boundary-scan architecture, instead of direct access via the IC pins. The boundary-scan chain performs serial/parallel conversion of test data. E-RPCT also provides I/O wrap to test non-contacted pins. The paper presents E-RPCT for full-scan design, as well as for full-scan core-based design.