Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
A method for generating weighted random test pattern
IBM Journal of Research and Development
IBM Journal of Research and Development
Boundary-scan design principles for efficient LSSD ASIC testing
IBM Journal of Research and Development
Design for testability and diagnosis in a VLSI CMOS System/370 processor
IBM Journal of Research and Development
Built-in self-test support in the IBM engineering design system
IBM Journal of Research and Development
Self-testing the 16-Mbps adapter chip for the IBM tokenring local area network
IBM Journal of Research and Development
Verity—a formal verification program for custom CMOS circuits
IBM Journal of Research and Development - Special issue: IBM CMOS technology
Test methodologies and design automation for IBM ASICs
IBM Journal of Research and Development
Design methodology for the S/390 parallel enterprise server G4 microprocessors
IBM Journal of Research and Development - Special issue: IBM S/390 G3 and G4
Functional verification of the CMOS S/390 parallel enterprise server G4 system
IBM Journal of Research and Development - Special issue: IBM S/390 G3 and G4
High-Density CMOS Multichip-Module Testing and Diagnosis
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Delay Test: The Next Frontier for LSSD Test Systems
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Test generation costs analysis and projections
DAC '80 Proceedings of the 17th Design Automation Conference
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
Design for Testability A Survey
IEEE Transactions on Computers
An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
IEEE Transactions on Computers
A New Representation for Faults in Combinational Digital Circuits
IEEE Transactions on Computers
Design methodology for the S/390 parallel enterprise server G4 microprocessors
IBM Journal of Research and Development - Special issue: IBM S/390 G3 and G4
Functional verification of the CMOS S/390 parallel enterprise server G4 system
IBM Journal of Research and Development - Special issue: IBM S/390 G3 and G4
Enhanced Reduced Pin-Count Test for Full-Scan Design
Journal of Electronic Testing: Theory and Applications
Testing the 500-MHz IBM S/390 Microprocessor
IEEE Design & Test
Microprocessor test and test tool methodology for the 500 MHz IBM S/390 G5 chip
ITC '98 Proceedings of the 1998 IEEE International Test Conference
99 % AC test coverage using only LBIST on the 1 GHz IBM S/390 zSeries 900 Microprocessor
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Enhanced Reduced Pin-Count Test for Full-Scan Design
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Testing The 400-MHz IBM Generation-4 CMOS Chip
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Diagnostic Techniques for the IBM S/390 600 MHz G5 Microprocessor
ITC '99 Proceedings of the 1999 IEEE International Test Conference
System performance management for the S/390 parallel enterprise server G5
IBM Journal of Research and Development
Structural and functional test of IBM system z10 chips
IBM Journal of Research and Development
Scalable and modular pervasive logic/firmware design
IBM Journal of Research and Development
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