A method for generating weighted random test pattern
IBM Journal of Research and Development
Boundary-scan design principles for efficient LSSD ASIC testing
IBM Journal of Research and Development
Built-in self-test support in the IBM engineering design system
IBM Journal of Research and Development
Intel 386TM EX Embedded Processor IDDQ Testing
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
An Experimental Chip to Evaluate Test Techniques: Experiment Results
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Delay Test: The Next Frontier for LSSD Test Systems
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
IDDQ Testing in CMOS Digital ASIC's - Putting it All Together
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Design of an Efficient Weighted-Random-Pattern Generation System
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
Advanced microprocessor test strategy and methodology
IBM Journal of Research and Development - Special issue: IBM S/390 G3 and G4
Enhanced Reduced Pin-Count Test for Full-Scan Design
Journal of Electronic Testing: Theory and Applications
Design Methodology for a Large Communication Chip
IEEE Design & Test
System-on-Chip Testability Using LSSD Scan Structures
IEEE Design & Test
Delay test of chip I/Os using LSSD boundary scan
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Microprocessor test and test tool methodology for the 500 MHz IBM S/390 G5 chip
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A Building Block BIST Methodology for SOC Designs: A Case Study
ITC '01 Proceedings of the 2001 IEEE International Test Conference
OPMISR: The Foundation for Compressed ATPG Vectors
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Enhanced Reduced Pin-Count Test for Full-Scan Design
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Addressing Early Design-For-Test Synthesis in a Production Environment
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Testing the Enterprise IBM System/390" Multi Processor
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Functional verification of a frequency-programmable switch chip with asynchronous clock sections
IBM Journal of Research and Development
DFT timing design methodology for at-speed BIST
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Blue Gene/L compute chip: control, test, and bring-up infrastructure
IBM Journal of Research and Development
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