DFT timing design methodology for at-speed BIST

Authors:
Yasuo Sato;Motoyuki Sato;Koki Tsutsumida;Masatoshi Kawashima;Kazumi Hatayama;Kazuyuki Nomoto
Affiliations:
Device Development Center, Hitachi, Ltd., Ome-shi, Tokyo, Japan;Device Development Center, Hitachi, Ltd., Ome-shi, Tokyo, Japan;Device Development Center, Hitachi, Ltd., Ome-shi, Tokyo, Japan;Device Development Center, Hitachi, Ltd., Ome-shi, Tokyo, Japan;Central Research Laboratory, Hitachi, Ltd., Kokubunji-shi, Tokyo, Japan;Semiconductor & Integrated Circuits, Hitachi, Ltd., Kodaira-shi, Tokyo, Japan
Venue:
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Year:
2003

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Abstract

Logic BIST is well known as an effective method for low cost testing. However, it is difficult to realize at-speed testing, as it requires a deliberate timing design in regard to logic design and layout of the chip. This paper presents a timing design methodology for at-speed BIST, using a multiple-clock domain scheme. Some experimental test results of large industrial designs using our custom fool "Singen", will also be shown.