TranGen: a SAT-based ATPG for path-oriented transition faults
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
DFT timing design methodology for at-speed BIST
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Evaluation of the statistical delay quality model
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
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This paper presents a practical coverage metric in delay testing,which is called a multiple-threshold gate-delay fault model, to obtain high quality tests for large circuits. Fault efficiencies for given multiple thresholds of the delay fault size are computed, and their entiretydescribes the quality of tests. Our approach guarantees that each gate-delay fault is not only robustly tested on almost the longest path, but also tested under the condition as a transition fault, by using two-pattern tests with a pattern-independent timing. We present procedures ofpath selection, fault simulation and test generation, where the path-status graph technique is used for an efficient computation. Experimental results for industrial circuits demonstrate that the proposed method can achieve high fault efficiencies for gate-delay faults having various fault sizes in a practical processing time.