Evaluation of the statistical delay quality model

Authors:
Yasuo Sato;Shuji Hamada;Toshiyuki Maeda;Atsuo Takatori;Seiji Kajihara
Affiliations:
Semiconductor Technology Academic Research Center, Yokohama, Japan;Semiconductor Technology Academic Research Center, Yokohama, Japan;Semiconductor Technology Academic Research Center, Yokohama, Japan;Semiconductor Technology Academic Research Center, Yokohama, Japan;Kyushu Institute of Technology, Iizuka, Japan
Venue:
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Year:
2005

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Abstract

In this paper we introduce a quality model that reflects fabrication process quality, design delay margin, and test timing accuracy. The model provides a measure that can predict the level of chip defects that cause delay failure, including marginal delay. We can therefore use the model to make test vectors that are effective in terms of both testing cost and chip quality. The results of experiments using ISCAS89 benchmark data and some large industrial design data reflect various characteristics of our statistical delay quality model.