BooleDozer: logic synthesis for ASICs
IBM Journal of Research and Development
Test methodologies and design automation for IBM ASICs
IBM Journal of Research and Development
Introduction to High-Level Synthesis
IEEE Design & Test
Introduction to the Scheduling Problem
IEEE Design & Test
Introducing Core-Based System Design
IEEE Design & Test
Timing Verification and the Timing Analysis program
DAC '82 Proceedings of the 19th Design Automation Conference
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The example chip operates with 14 externally provided system clocks plus four clocks recovered from input data streams and 36 corresponding internal clock domains, it also couples a large digital design to a mixed-signal part in physical design